PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
µ
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Preface
The PowerPC 740 and PowerPC 750 are members of the PowerPC
family of reduced instruction set
computer (RISC) microprocessors. The PPC740L and PPC750L microprocessors are the PID-8p implemen-
tations of the PowerPC 740 and PowerPC 750 in IBM CMOS 7S 0.20
µm
copper technology. They are
referred to in the body of this document as “740“ and “750.”
Information in this document does not apply to implementations of the PowerPC 740 and PowerPC 750 in
other technologies, such as the PID-8t.
The information in this document is also specific to revision level dd3.2 of the (PID-8p) PPC740L and
PPC750L, and does not apply to previous revisions.
This document is generally written in terms of the 750. Unless otherwise noted, information that applies to the
750 also applies to the 740. Exceptions are detailed.
The 740 uses the same die as the 750, but the 740 does not bring the L2 cache interface out to external
package pins.
New Features for dd3.x
• Selectable I/O voltages on 60X bus and L2 bus. See ”Recommended Operating Conditions,” on page 11.
Older revs must leave these pins “no connect” or “tied high” for 3.3v I/Os. AC timings are the same for all
I/O voltages modes unless otherwise noted.
• 60X bus:core frequency ratios now also support the 10x ratio. See ”PLL Configuration,” on page 40.
• Extra output hold on the 60x bus by L2_TSTCLK pin tied low is no longer available. The L2_TSTCLK pin
must now be tied to OV
DD
for normal operation. See ”60X Bus Output AC Timing Specifications for the
1
Page 5
Version 2.0
9/6/2002
IBM [ IBM ]
