IBM25PPC750L-FB0B450W 参数 Datasheet PDF下载

PowerPC 750 SCM RISC Microprocessor

PID8p-750

Preliminary Copy

Overview

The PID8p-750 is targeted for high performance, low power systems and supports the following power man-

agement features: doze, nap, sleep, and dynamic power management. The PID8p-750 consists of a proces-

sor core and an internal L2 Tag combined with a dedicated L2 cache interface and a 60x bus.

Figure 1. PID8p-750 Block Diagram

Control Unit

Completion

Instruction Fetch

Branch Unit

32K ICache

System

Unit

Dispatch

BHT /

BTIC

GPRs

FXU1

FXU2

Rename

Buffers

LSU

FPRs

FPU

Rename

Buffers

32K DCache

L2 Tags

L2 Cache

BIU

60X

BIU

Page 2

Version 2.0

Datasheet

9/30/99