PowerPC 750 SCM RISC Microprocessor
PID8p-750
Preliminary Copy
System Design Information
This section provides electrical and thermal design recommendations for successful application of the PID8p-
750.
PLL Configuration
The PID8p-750 PLL is configured by the PLL_CFG[0-3-] signals. For a given SYSCLK (bus) frequency, the
PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for
the PID8p-750 is shown in the following table for nominal frequencies.
PID8p-750 Microprocessor PLL Configuration
PLL_CFG
(0:3)
Processor to Bus VCO Divider
Frequency Range Supported by VCO having an example range of
VCOmin7 = 400 to VCOmax =1000 MHz6
Frequency Ratio
(r)
(d)
SYSCLK
Min = VCO /(r*d) Max = VCO
Core
/(r*d) Min = VCO /d Max = VCO
bin
dec
0
/d
max
min
max
min
1
0000
n/a
n/a
n/a
n/a
n/a
Rsv
0001
0010
0011
1
2
3
7.5x
7x
2
2
27
29
66
71
200
500
3
n/a
n/a
n/a
n/a
n/a
n/a
n/a
PLL Bypass
1
0100
4
n/a
n/a
n/a
Rsv
0101
0110
5
6
6.5x
2
2
31
252
44
77
50
200
200
500
500
8
10x
5
0111
1000
7
8
4.5x
3x
2
2
200
500
100
5
66
100
91
1001
1010
9
5.5x
4x
2
2
36
50
5
10
100
1011
1100
11
12
5x
8x
2
2
40
100
63
252
33
1101
1110
13
14
6x
2
2
83
5
3.5x
57
100
n/a
4
1111
15
n/a
n/a
Off
Off
Off
Note:
1. Reserved settings.
2. SYSCLK min is limited by the lowest frequency that manufacturing will support, see Section , “Clock AC Specifications,” for valid SYSCLK and VCO
frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode
operation. This mode is intended for factory use only. Note: The AC timing specifications given in the document do not apply in PLL-bypass mode.
4. In Clock - off mode, no clocking occurs inside the PID8p-750 regardless of the SYSCLK input.
5. The SYSCLK limit is 100MHz as specified in Section “Clock AC Specifications,” on page 10.
6. VCOMAX is specified in this table by the maximum core processor speed. See “Clock AC Specifications” on page 10. This is not the VCO limit of the
technology.
7. VCOMIN is specified in this table by the minimum core processor speed. See “Clock AC Specifications” on page 10.
8. Available on rev level DD3.x or higher
Page 30
Version 2.0
Datasheet
9/30/99
IBM [ IBM ]
