PowerPC 750 SCM RISC Microprocessor
Preliminary Copy
PID8p-750
Preface
TM
The PowerPC PID8p-750 microprocessor is an implementation of the PowerPC family of reduced instruc-
tion set computer (RISC) microprocessors. In this document, the term “PID8p-750” is used as an abbreviation
for the phrase “PowerPC 750 SCM RISC Microprocessor Family: PID8p-750 microprocessor.”
This document contains pertinent physical characteristics of the PID8p-750 Single Chip Modules (SCM) and
covers the following topics:
Topic
• Overview (page 2)
• Features (page 3)
• General Parameters (page 5)
• Electrical and Thermal Characteristics (page 6)
• PowerPC PID8p-750 Microprocessor Pin Assignments (page 23)
• PowerPC PID8p-750 Microprocessor Pinout Listings (page 24)
• PowerPC PID8p-750 Microprocessor Package Description (page 27)
• System Design Information (page 30)
• Ordering Information (page 40)
New features/deletions for rev level dd3.x:
• Selectable I/O voltages on 60X bus (pin W1) and L2 bus (pin A19). See Table , “Recommended Operating
Conditions1,2,3,” on page 6. Older revs must leave these pins “no connect” or “tied high” for 3.3v I/Os. AC
timings are the same for all I/O voltage modes unless otherwise noted. The 1.8v I/O is selected by tying
the I/O select pin to ground. If a pull down resistor is necessary, the resistor value must be no more than
10 ohms.
• 60X bus to core frequency now also supports the 10x ratio. See Table , “PID8p-750 Microprocessor PLL
Configuration,” on page 30 for how to set this ratio.
• Extra output hold on the 60X bus by L2_TSTCLK pin tied low is no longer available. The L2_TSTCLK pin
1
must now be tied to OV for normal operation. See Table , “60X Bus Output AC Timing Specifications ,”
DD
on page 13.
9/30/99
Version 2.0
Datasheet
Page 1
IBM [ IBM ]
