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IBM25PPC750L-EB0B375W 参数 Datasheet PDF下载

IBM25PPC750L-EB0B375W图片预览
型号: IBM25PPC750L-EB0B375W
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 375MHz, CMOS, CBGA360, 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360]
分类和应用: 时钟外围集成电路
文件页数/大小: 46 页 / 610 K
品牌: IBM [ IBM ]
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PowerPC 750 SCM RISC Microprocessor  
PID8p-750  
Preliminary Copy  
PowerPC PID8p-750 Microprocessor Pinout Listings  
The following table provides the pinout listing for the 360 CBGA package (the PID8p-750).  
5
Pinout Listing for the 360 CBGA package  
Signal Name  
A0-A31  
Pin Number  
Active  
High  
I/O  
I/O  
A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3, G6, H2, E2,  
L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3, H3, J2, J6, K3, K2, L2  
AACK  
ABB  
N3  
Low  
Low  
High  
Input  
I/O  
L7  
8
C4, C5, C6, C7  
I/O  
AP0-AP3  
ARTRY  
L6  
A8  
Low  
I/O  
9
AVDD  
BG  
H1  
E7  
D7  
C2  
B8  
E3  
K5  
G1  
K1  
D1  
Low  
Low  
Low  
Low  
Low  
--  
Input  
Output  
Output  
Output  
Input  
Output  
I/O  
BR  
CKSTP_OUT  
CI  
CKSTP_IN  
CLKOUT  
DBB  
Low  
Low  
Low  
Low  
High  
DBDIS  
DBG  
Input  
Input  
Input  
I/O  
DBWO  
DH0-DH31  
W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9, W9, R10,  
W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, U5, W4, P7, V5, V4, W3,  
U4, R5  
DL0-DL31  
M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13, U12, P12, T13,  
W13, U13, V10, W8, T11, U11, V12, V8, T1, P1, V1, U1, N1, R2, V3,  
U3, W2  
High  
High  
I/O  
I/O  
8
L1, P2, M2, V2, M1, N2, T3, R1  
DP0-DP7  
DRTRY  
GBL  
H6  
B1  
Low  
Low  
Input  
I/O  
Note:  
1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.  
2. OVDD inputs supply power to the I/O drivers and VDD inputs supply power to the processor core.  
3. Internally tied to L2OVDD in the PID8p-750 360 CBGA package. This is NOT a supply pin.  
4. These pins are reserved for potential future use as additional L2 address pins.  
5. Pull up and pull down resistor requirements for all pins are listed in the “Pull-up / Pull-down Resistor Requirements” section on page 33  
6. BVSEL selects the I/O voltage on the 60X bus. L2VSEL selects the I/O voltage on the L2 bus. Please refer to the Table “Recommended Operating  
Conditions1,2,3,” on page 6, for the use of these pins.  
7. TCK must be tied high or low for normal machine operation.  
8. Address and data parity signals must be tied high or low if unused in the design.  
9. Starting with rev levels dd3.X, the AVDD pin is no longer brought out to the package.  
Page 24  
Version 2.0  
Datasheet  
9/30/99