PowerPC 750 SCM RISC Microprocessor
PID8p-750
Preliminary Copy
60x Bus Output AC Specifications
The following table provides the 60x bus output AC timing specifications for the PID8p-750 as defined in
Figure 5. Output timing specification for the L2 bus are provided in the Section “L2 Bus Output AC Specifica-
tions,” on page 18.
60X Bus Output AC Timing Specifications1
See Table “Recommended Operating Conditions1,2,3,” on page 6 for operating conditions, CL = 50pF2
Num
Characteristic
300, 333, 350, 366,
Unit
Notes
375, 400, 433, 450, 466, 500MHz
Minimum
Maximum
12
13
14
SYSCLK to Output Driven (Output Enable Time)
0.5
–
ns
ns
ns
8
5
5
SYSCLK to Output Valid (TS, ABB, ARTRY, DBB, and TBST)
4.5
5.0
SYSCLK to all other Output Valid (all except TS, ABB, ARTRY,
DBB, and TBST)
–
15
16
SYSCLK to Output Invalid (Output Hold)
1.0
–
ns
ns
3, 8, 9
8
SYSCLK to Output High Impedance (all signals except ABB,
ARTRY, and DBB)
6.0
17
18
19
20
21
SYSCLK to ABB and DBB high impedance after precharge
SYSCLK to ARTRY high impedance before precharge
SYSCLK to ARTRY precharge enable
–
1.0
5.5
tSYSCLK
ns
4, 6, 8
8
–
0.2×tSYSCLK + 1.0
ns
3, 4, 7
4, 7
Maximum delay to ARTRY precharge
1
2
tSYSCLK
tSYSCLK
SYSCLK to ARTRY high impedance after precharge
4, 7, 8
Note:
1. All output specifications are measured from the midpoint voltage of the rising edge of SYSCLK to the midpoint voltage of the signal in question. Both
input and output timings are measured at the pin. Midpoint voltage (VM) is 1.4v for OVdd in 3.3v mode and OVDD/2 for all other I/O modes.
2. All maximum timing specifications assume CL = 50pF.
3. This minimum parameter assumes CL = 0pF.
4. tSYSCLK is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of
SYSCLK to compute the actual time duration of the parameter in question.
5. Output signal transitions from GND to 2.0V or OVDD to 0.8V.
6. Nominal precharge width for ABB and DBB is 0.5 tSYSCLK
7. Nominal precharge width for ARTRY is 1.0 tSYSCLK
8. Guaranteed by design and characterization, and not tested.
9. L2_TSTCLK should be tied to OVDD
.
.
.
9/30/99
Version 2.0
Datasheet
Page 13
IBM [ IBM ]
