PowerPC 750FL RISC Microprocessor
Preliminary
5.2 PLL Power Supply Filtering
The 750FL microprocessor has two separate AV signals (A1V and A2V ) that provide power to the
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clock generation phase-locked loops.
Most designs are expected to use a single PLL configuration mode throughout the application. These type of
designs must use the default configuration, A1V (PLL0), and tie the A2V (PLL1) signal to ground
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(AGND) through a 100 Ω resistor. This is shown Figure 5-1 Single PLL Power Supply Filter Circuit with
A1VDD Pin and A2VDD Pin Tied to GND on page 43.
For designs planning to optimize power savings through dynamic switching between these dual PLL circuits,
it is recommended, though not required, that each AV have a separate voltage input and filter circuit.
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To ensure the stability of the internal clock, the power supplied to the AV input signals must be filtered
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using a circuit similar to the one shown in Figure 5-1 on page 43. The circuit must be placed as close as
possible to the AV pin to ensure that it filters out as much noise as possible.
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For descriptions of the sample PLL power supply filtering circuits, see Table 5-3.
Table 5-3. Sample PLL Power Supply Filtering Circuits
Samples of PLL Power Supply Filtering Circuits
Number of
Ferrite
Recommended
Circuit Design
Circuit Description
Filtering
Circuits
Circuit Figure
Notes
Beads
Single PLL circuit configuration that uses the A1VDD
and ties the A2VDD pin to GND
1
1
2
1
1
2
Figure 5-1 on page 43
Figure 5-2 on page 44
Figure 5-3 on page 45
Yes
Optional
Yes
Single PLL circuit configuration that uses both the
A1VDD and the A2VDD pins and a single ferrite bead
1, 2
2, 3
Dual PLL configuration that uses a separate circuit
for the A1VDD pin and for the A2VDD the pin
Notes:
1. Optional configurations are supported, though not recommended.
2. This circuit design can be used with the dual PLL feature enabled, though optimum power savings might not be realized.
For additional information, see Figure 5-3 Dual PLL Power Supply Filter Circuits on page 45.
3. This circuit design can be used with the dual PLL feature enabled to optimize power savings.
System Design Information
Page 42 of 65
750flds60.fm.6.0
April 27, 2007
IBM [ IBM ]
