PowerPC 750FL RISC Microprocessor
Preliminary
5.6 64- or 32-Bit Data Bus Mode
This mode selection varies for different design revision (DD) levels. For the 750FL DD2.X, mode setting is
determined by the state of the mode signal, TLBISYNC, at the transition of HRESET from low to high. If TLBI-
SYNC is high when HRESET makes the transition from active to inactive, 64-bit mode is selected. If TLBI-
SYNC is low when HRESET makes the transition from active to inactive, 32-bit mode is selected.
Special Note: (Reduced-pinout mode) To make the transition from a previous processor with reduced-
pinout mode, drive TLBISYNC appropriately, leave the DP(0:7) and AP(0:3) pins floating, and
disable parity checking. The 750FL microprocessor does not have APE and DPE pins.
5.7 I/O Voltage Mode Selection
Selection between 1.8 V, 2.5 V, or 3.3 V I/O modes is accomplished by using the BVSEL and L1_TSTCLK
pins:
• If BVSEL = 1 and L1_TSTCLK = 0, then the 3.3 V mode is enabled.
• If BVSEL = 1 and L1_TSTCLK = 1, then the 2.5 V mode is enabled.
• If BVSEL = 0 and L1_TSTCLK = 1, then the 1.8 V mode is enabled.
Note: Setting both BVSEL and L1_TSTCLK low is not a valid bus mode configuration.
Table 5-7. Summary of Mode Select
Mode
750FL
32-bit mode
Sample TLBISYNC to select
High = 64-bit mode
Low = 32-bit mode
I/O mode selection
3.3 V 165 mV (BVSEL = 1, L1_TSTCLK = 0) or
2.5 V 125 mV (BVSEL = 1, L1_TSTCLK = 1) or
1.8 V 100 mV (BVSEL = 0, L1_TSTCLK = 1)
5.8 Thermal Management
This section provides thermal management information for the CBGA package for air-cooled applications.
Correct thermal control design depends primarily upon the system-level design; that is, the heat sink selec-
tion, air flow rate, and the thermal interface material. To reduce the die junction temperature, heat sinks can
be attached to the package by several methods: adhesive, spring clips to holes in the printed circuit board or
package, mounting clip, or a screw assembly. See Figure 5-10 Exploded Cross-Sectional View of Package
with Several Heat Sink Options on page 61 for more information.
In general, a heat sink is required for all 750FL applications.
A design example is included in this section.
System Design Information
Page 56 of 65
750flds60.fm.6.0
April 27, 2007
IBM [ IBM ]
