PowerPC 750FL RISC Microprocessor
Preliminary
4.4 Pinout Listings
Table 4-1 contains the pinout listing for the 750FL microprocessor CBGA package.
Table 4-1. Pinout Listing for the CBGA Package (Sheet 1 of 3)
Signal Name
Pin Number
Active
High
Input/Output
Input/Output
Notes
E20, E19, D20, C20, D19, C19, A20, E16, B20, E17,
B18, A18, A17, A19, A16, B16, B10, B9, A9, B7, A7,
D8, A5, B6, D7, D5, B5, B4, A4, A3, B3, E5.
A[0:31]
A1VDD
A2VDD
AACK
ABB
Y15
Y16
A8
Low
Low
Input
Y6
Input/Output
AGND
AP[0:3]
ARTRY
BG
Y14
D16, D13, A13, B8
High
Low
Low
Input/Output
Input/Output
Input
6
W7
W4
Y1, Y2
Y3
BLANK
BR
3
4
Low
Output
Input
BVSEL
W9
Y12
T4
CHECKSTOP (CKSTP_OUT)
Low
Low
Low
High
Low
Low
Low
Low
Output
Output
Input
CI
CKSTP_IN
CLK_OUT
DBB
Y10
T5
Output
Input/Output
Input
U7
DBDIS
DBG
A10
Y5
Input
DBWO
A6
Input
W18, T17, Y20, Y19, W20, V19, U19, T16, T19, U20,
V20, R19, N17, P17, R20, P20, N20, P19, M20, L20,
M19, L19, K20, J19, K19, G20, H20, H17, H19, F19,
G17, F20
DH[0:31]
DL[0:31]
High
High
Input/Output
Input/Output
A2, A1, C2, E4, C1, E2, D2, E1, D1, F1, G2, F2, H2,
H4, G1, K2, J2, K1, J1, L2, M2, L1, N2, N4, N1, P1, P4,
P2, R2, R1, U2, T1
DP[0:7]
DRTRY
Notes:
T20, N19, J20, G19, B1, G4, H1, M1
W3
High
Low
Input/Output
Input
6
1. These are test signals for factory use only and must be pulled up to OVDD for normal system operation.
2. OVDD supplies power to the input/output drivers and VDD supplies power to the processor core.
3. These pins are reserved.
4. BVSEL and L1_TSTCLK select the input/output voltage mode on the 60x bus (see Section 5.7 I/O Voltage Mode Selection on
page 56).
5. TCK must be tied high or low for normal system operation.
6. Address and data parity must be left floating if unused in the design.
Dimensions and Signal Assignments
Page 32 of 65
750flds60.fm.6.0
April 27, 2007
IBM [ IBM ]
