DD 2.X
PowerPC 750FX RISC Microprocessor
Preliminary
TM
Figure 5-7. IBM RISCWatch JTAG to HRESET, TRST, and SRESET Signal Connector
HRESET from RISCWatch
HRESET to PowerPC 750FX
System HRESET
TRST to PowerPC 750FX
TRST from RISCWatch
SRESET from RISCWatch
SRESET to PowerPC 750FX
System SRESET
Note: See notes for Table 5-6 Input-Output Usage on page 44.
5.5 Level Protection
A level protection feature is included in the PowerPC 750FX RISC Microprocessor. The level protection
feature is available in the 1.8V, 2.5V, and 3.3V bus modes. This feature prevents ambiguous floating refer-
ence voltages by pulling the respective signal line to the last valid or nearest valid state.
For example, if the Input/Output voltage level is closer to OVDD, the circuit pulls the I/O level to OVDD. If the I/O
level is closer to GND, the I/O level is pulled low. This self-latching circuitry keeps the floating inputs defined
and avoids meta-stability. In Table 5-6 Input-Output Usage on page 44, these signals are defined as keeper
in the Level Protect column.
Keepers are not intended to force a net to a particular state. The keeper supplies a small (100 µA max.)
amount of current, which is intended to help keep a net at the current logic state.
The level protect circuitry provides no additional leakage current to the signal I/O; however, some amount of
current must be applied to the keeper node to overcome the level protection latch. This current is process
dependent, but in no case is the current required over 100µA.
This feature allows the system designer to limit the number of resistors in the design and optimize placement
and reduce costs.
Note: Having a level protection (keeper) on the associated signal I/O does not replace a pull-up or pull-down
resistor that is needed by the 750FX or a separate device located on the 60x bus. The designer must supply
any such resisters.
5. System Design Information
Page 48 of 63
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
IBM [ IBM ]
