DD 2.X
Preliminary
PowerPC 750FX RISC Microprocessor
4.4 Pinout Listings
Table 4-1 contains the pinout listing for the 750FX CBGA package.
Table 4-1. Pinout Listing for the CBGA package
Signal Name
Pin Number
Active
High
Input/Output
Input/Output
Notes
E20, E19, D20, C20, D19, C19, A20, E16, B20, E17,
B18, A18, A17, A19, A16, B16, B10, B9, A9, B7, A7,
D8, A5, B6, D7, D5, B5, B4, A4, A3, B3, E5.
A[0:31]
A1VDD
Y15
—
—
—
—
A2VDD
Y16
AACK
A8
Low
Low
—
Input
ABB
Y6
Input/Output
—
AGND
Y14
AP[0:3]
D16, D13, A13, B8
High
Low
Low
—
Input/Output
Input/Output
Input
6
ARTRY
W7
W4
Y1, Y2
Y3
BG
BLANK
—
3
4
BR
Low
—
Output
Input
BVSEL
W9
Y12
T4
CHECKSTOP (CKSTP_OUT)
Low
Low
Low
High
Low
Low
Low
Low
Output
Output
Input
CI
CKSTP_IN
CLK_OUT
DBB
Y10
T5
Output
Input/Output
Input
U7
DBDIS
DBG
A10
Y5
Input
DBWO
A6
Input
W18, T17, Y20, Y19, W20, V19, U19, T16, T19, U20,
V20, R19, N17, P17, R20, P20, N20, P19, M20, L20,
M19, L19, K20, J19, K19, G20, H20, H17, H19, F19,
G17, F20
DH[0:31]
DL[0:31]
High
High
Input/Output
Input/Output
A2, A1, C2, E4, C1, E2, D2, E1, D1, F1, G2, F2, H2,
H4, G1, K2, J2, K1, J1, L2, M2, L1, N2, N4, N1, P1, P4,
P2, R2, R1, U2, T1
DP[0:7]
DRTRY
GBL
T20, N19, J20, G19, B1, G4, H1, M1
High
Low
Low
Input/Output
Input
6
W3
W1
Input/Output
Notes:
1. These are test signals for factory use only and must be pulled up to OV for normal machine operation.
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2. OV inputs supply power to the Input/Output drivers and V inputs supply power to the processor core.
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3. These pins are reserved for potential future use.
4. BVSEL and L1_TSTCLK select the Input/Output voltage mode on the 60x bus (see Section 5.7 on page 49).
5. TCK must be tied high or low for normal machine operation.
6. Address and data parity should be left floating if unused in the design.
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
4. Dimensions and Signal Assignments
Page 25 of 63
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