Data Sheet
Preliminary
PowerPC® 750CXe RISC Microprocessor
6.6.3 Internal Package Conduction Resistance
For the PBGA, described in Table 4-3 on page 8, the primary intrinsic conduction thermal resistance paths
are as follows.
• Die junction-to-case thermal resistance θJC
• Die junction-to-lead thermal resistance θJB
• Die junction-to-ambient thermal resistance θJA
Figure 6-4 depicts the primary heat transfer path for this package.
Figure 6-4. PBGA Package Thermal Model
External Resistance
Radiation
Convection
θJA
Die/Case (θJC
Chip Junction
)
Internal Resistance
Package/Leads (θJB
)
Printed-Circuit Board
Radiation
(Note the internal versus external package resistance.)
Convection
External Resistance
6.7 Operational and Design Considerations
6.7.1 Level Protection
A level protection feature is included in the PowerPC 750CXe in releases DD2.0 and later. The level
protection feature is available only in the 1.8V bus mode. This feature prevents ambiguous floating reference
voltages by pulling the respective signal line to the last valid or nearest valid state.
For example, if the I/O voltage level is closer to OVDD, the circuit pulls the I/O level to OVDD; if the I/O level is
closer to GND, the I/O level is pulled low. This self-latching circuitry “keeps” the floating inputs defined and
avoids meta-stability. In Table 6-3, these signals are defined as “Keeper” in the Level Protect column.
750cxe_DD3.1_Dev_3_gen_mkt.fm.1.5
April 8, 2004
System Design Information
Page 33 of 36
IBM [ IBM ]
