Data Sheet
Preliminary
PowerPC® 750CXe RISC Microprocessor
Table of Contents
List of Tables ................................................................................................................. iii
List of Figures ................................................................................................................ v
1. General Information .................................................................................................... 1
1.1 Features ........................................................................................................................................... 1
1.2 Special Design Level Considerations/Features ........................................................................... 3
1.3 Ordering Information ...................................................................................................................... 3
1.4 Processor Version Register (PVR) ................................................................................................ 4
2. Overview ...................................................................................................................... 5
2.1 PowerPC 750CXe Block Diagram .................................................................................................. 5
3. General Parameters .................................................................................................... 6
4. Electrical and Thermal Characteristics ..................................................................... 7
4.1 DC Electrical Characteristics ......................................................................................................... 7
4.2 AC Electrical Characteristics ....................................................................................................... 10
4.2.1 Clock AC Specifications ........................................................................................................ 10
4.3 Spread Spectrum Clock Generator (SSCG) ................................................................................ 11
4.4 60x Bus Input AC Specifications ................................................................................................. 12
4.5 60x Bus Output AC Specifications .............................................................................................. 13
4.5.1 IEEE 1149.1 AC Timing Specifications ................................................................................. 16
5. PowerPC 750CXe Dimension and Physical Signal Assignments ........................ 18
6. System Design Information ..................................................................................... 26
6.1 PLL Configuration ......................................................................................................................... 26
6.2 PLL Power Supply Filtering ......................................................................................................... 27
6.3 Decoupling Recommendations ................................................................................................... 27
6.4 Connection Recommendations ................................................................................................... 28
6.5 Output Buffer DC Impedance ....................................................................................................... 28
6.5.1 Input-Output Usage ............................................................................................................... 29
6.6 Thermal Management Information .............................................................................................. 32
6.6.1 Thermal Assist Unit ............................................................................................................... 32
6.6.2 Heat Sink Considerations ...................................................................................................... 32
6.6.3 Internal Package Conduction Resistance .............................................................................. 33
6.7 Operational and Design Considerations ..................................................................................... 33
6.7.1 Level Protection ..................................................................................................................... 33
6.7.2 64- or 32-Bit Data Bus Mode ................................................................................................. 34
6.7.3 60x Bus Operation ................................................................................................................. 34
6.7.4 DBWO/L2_TSTCLK ............................................................................................................... 34
6.7.5 CHKSTP_OUT/CLKOUT ....................................................................................................... 34
750cxe_TOC.fm.1.5
April 8, 2004
Page i of 36
IBM [ IBM ]
