Data Sheet
PowerPC® 750CXr RISC Microprocessor
Preliminary
• Floating-point unit (continued)
- Hardware support for divide
- Hardware support for denormalized
numbers
- Virtual memory support for up to 4 PB (252)
virtual memory
- Real memory support for up to 4 GB (232) of
physical memory
- Time deterministic non-IEEE mode
- Support for big/little-endian addressing
• System unit
• Level 2 (L2) cache
- Executes CR logical instructions and
miscellaneous system instructions
- Special register transfer instructions
- Internal L2 cache controller and 4KB-entry
tags; 256KB data SRAMs
- Copy-back or write-through data cache on a
page basis, or for all L2
- 64-byte sectored line size
- L2 frequency at core speed
- On-board ECC
• L1 Cache structure
- 32KB, 32-byte line, 8-way set associative
instruction cache
- 32KB, 32-byte line, 8-way set associative
data cache
• Bus interface
- Single-cycle cache access
- Pseudo-LRU replacement
- Copy-back or write-through data cache (on
a page per page basis)
- Compatible with 60x processor interface
(some pin functions removed, see Table 5-2
on page 31)
- 32-bit address bus
- 3-state (MEI) memory coherency
- Hardware support for data coherency
- Non-blocking instruction and data cache
(one outstanding miss under hits)
- No snooping of instruction cache
- 64-bit data bus (also supports 32-bit mode)
- Core-to-bus frequency multipliers of 2.5x,
3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x,
supported
• Power
• Memory management unit
- 128-entry, 2-way set associative instruction
TLB
- 6W typical @ 400MHz
• Testability
- LSSD scan design
- 128-entry, 2-way set associative data TLB
- Hardware reload for TLBs
- 4 instruction BATs and 4 data BATs
- Powerful diagnostic and test interface
through Common On-Chip Processor (COP)
and IEEE 1149.1 (JTAG) interface
General Information
Page 10 of 43
750cxr_DD4.0_Dev_gen_4_mkt.fm
February 28, 2005
IBM [ IBM ]
