Data Sheet
PowerPC® 750CXr RISC Microprocessor
Preliminary
The level protect circuitry provides no additional leakage current to the signal I/O; however, some amount of
current must be applied to the “keeper” node to overcome the level protection latch. This current is process
dependent, but in no case is the current required over 100µA.
This feature allows the system designer to limit the number of resistors in the design and optimize placement
and reduce costs.
6.7.2 64- or 32-Bit Data Bus Mode
Typical operation is considered to be in 64-bit Data Bus mode. Mode setting is determined by the state of the
mode signal (QACK) at the transition of HRESET from its active to inactive state (low to high). If QACK is low
when HRESET transitions from active to inactive, 64-bit mode is selected. If QACK is high when HRESET
transitions from active to inactive, 32-bit mode is selected.
6.7.3 60x Bus Operation
Selection between 1.8V and 2.5V I/O is accomplished using the BVSEL pin. If BVSEL is set low then the
1.8V mode is enabled. If BVSEL is set high, then the 2.5V mode is enabled.
6.7.4 DBWO/L2_TSTCLK
One pin has two functions: DBWO and L2_TSTCLK dependent upon the LSSD_MODE pin. When the
LSSD_MODE pin is low, the DBWO/L2_TSTCLK pin is set to L2_TSTCLK function which is used during the
manufacturing process for testing.
When the LSSD_MODE pin is pulled to the high state, the DBWO/L2_TSTCLK pin is set to DBWO which is
identical to those descriptions given in earlier versions of the PowerPC® 750CXr RISC Microprocessor User’s
Manuals.
6.7.5 CHKSTP_OUT/CLKOUT
CHKSTP_OUT/CLKOUT share a common pin. CHKSTP_OUT is the normal function of this pin.
The system clock or processor clock may be viewed by setting the appropriate bits in Hardware
Implementation-Dependent Register 0.
System Design Information
Page 42 of 43
750cxr_DD4.0_Dev_gen_4_mkt.fm
February 28, 2005
IBM [ IBM ]
