IBM25PPC740-DB0M2500 参数 Datasheet PDF下载

PowerPC 750

TM

SCM RISC Microprocessor

Preliminary Copy

Overview

The 750 is targeted for high performance, low power systems and supports the following power management

features; doze, nap, sleep, and dynamic power management. The 750 consists of a processor core and an

internal L2 Tag combined with a dedicated L2 cache interface and a 60x bus. Figure 8 shows a block diagram

of the 750.

Figure 8. 750 Block Diagram.

Control Unit

Completion

Instruction Fetch

Branch Unit

32K ICache

System

Unit

Dispatch

BHT /

BTIC

GPRs

FXU1

FXU2

Rename

Buffers

LSU

FPRs

FPU

Rename

Buffers

32K DCache

L2 Tags

L2 Cache

BIU

60X

BIU

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Datasheet

7/15/99