Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Notes: 1. In all of the following I/O Specifications tables a timing values of na means “not applicable” and dc
means “don’t care.”
2. See “Test Conditions” on page 59 for output capacitive loading.
I/O Specifications—Group 1 (Part 1 of 3)
Notes:
1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz
and 2ns for 33.33MHz.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OV and I/O L is specified at 0.1OV . For all other interfaces, I/O H is specified at
DD
DD
2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
I/O H
(min)
I/O L
(min)
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
PCI Interface
PCIAD31:0
PCIC3:0[BE3:0]
PCIClk
3
3
0
0
6
6
1
1
0.5
0.5
na
1.5
1.5
na
PCIClk
PCIClk
1
1
async
1
dc
3
dc
0
na
1
PCIDevSel
PCIFrame
6
6
0.5
0.5
1.5
1.5
PCIClk
PCIClk
3
0
1
1
PCIGnt0[Req]
PCIGnt1:5
na
na
6
1
0.5
1.5
PCIClk
1
PCIIDSel
3
na
3
0
na
0
6
dc
6
1
dc
1
na
0.5
0.5
0.5
0.5
na
1.5
1.5
1.5
1.5
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
1
PCIINT[PerWE]
PCIIRDY
async
1
1
1
PCIParity
PCIPErr
3
0
6
1
3
0
6
1
PCIReq0[Gnt]
PCIReq1:5
5
0
na
na
na
na
PCIClk
1
PCIReset
na
na
3
na
na
0
na
na
6
na
na
1
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
PCIClk
PCIClk
PCIClk
PCIClk
PCISErr
PCIStop
1
1
PCITRDY
3
0
6
1
Ethernet Interface
EMCMDClk
na
na
0
settable
2
10.3
10.3
7.1
7.1
2, async
2
1 OPB clock 1 OPB clock
period + 10ns
EMCMDIO[PHYMDIO]
100
EMCMDClk
period
EMCTxD3:0
EMCTxEn
EMCTxErr
PHYCol
na
na
na
na
na
na
20
20
20
2
2
2
10.3
10.3
10.3
10.3
10.3
na
7.1
7.1
7.1
7.1
7.1
na
PHYTX
PHYTX
PHYTX
2
2
2
2, async
2, async
2, async
2
PHYCrS
PHYRxClk
PHYRxD3:0
PHYRxDV
PHYRxErr
PHYTxClk
4
4
4
1
1
1
na
na
na
na
na
na
10.3
10.3
10.3
na
7.1
7.1
7.1
na
PHYRX
PHYRX
PHYRX
2
2
2, async
46
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