Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 9 of 10)
Signal Name
Ball
Interface Group
Page
C25
E23
E24
Y23
Y26
Other
Reserved
37
Note: AF4 must be tied to OV or GND. All other reserved pins should be left
unconnected.
DD
1
AF4
Req[PCIGnt0]
SysClk
SysErr
SysReset
TCK
U23 PCI
30
35
35
35
35
35
35
35
35
35
35
A25 System
AD25 System
D22 System
AD22 JTAG
AE24 JTAG
AD23 JTAG
D26 System
D24 System
AC22 JTAG
AE26 JTAG
TDI
TDO
TestEn
TmrClk
TMS
TRST
[TS1E]GPIO1
[TS2E]GPIO2
[TS1O]GPIO3
[TS2O]GPIO4
[TS3]GPIO5
[TS4]GPIO6
[TS5]GPIO7
[TS6]GPIO8
[TrcClk]GPIO9
D18
C20
A22
AF18
AC9 System
AE8
AF5
AC7
35
AB3
UART0_CTS
AB4 Internal Peripheral
AE18 Internal Peripheral
AE3 Internal Peripheral
AF2 Internal Peripheral
AD15 Internal Peripheral
AD16 Internal Peripheral
AE16 Internal Peripheral
AF3 Internal Peripheral
AC3 Internal Peripheral
AC3 Internal Peripheral
AD2 Internal Peripheral
AD2 Internal Peripheral
AC1 Internal Peripheral
AC2 Internal Peripheral
AE17 Internal Peripheral
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
UART0_DCD
UART0_DSR
UART0_DTR
UART0_RI
UART0_RTS
UART0_Rx
UART0_Tx
UART1_CTS/UART1_DSR
UART1_DSR/UART1_CTS
UART1_DTR/UART1_RTS
UART1_RTS/UART1_DTR
UART1_Rx
UART1_Tx
UARTSerClk
23
IBM [ IBM ]
