Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Peripheral Interface Clock Timings
Parameter
Min
Note 1
15
Max
66.66
Note 1
33.33
40
Units
MHz
ns
PCIClk input frequency (asynchronous mode)
PCIClk period (asynchronous mode)
PCI Clock frequency (synchronous mode)
PCI Clock period (synchronous mode - Note 2)
PCIClk input high time
25
MHz
ns
30
40% of nominal period 60% of nominal period
40% of nominal period 60% of nominal period
ns
PCIClk input low time
ns
EMCMDClk output frequency
EMCMDClk period
–
2.5
–
MHz
ns
400
EMCMDClk output high time
EMCMDClk output low time
PHYTxClk input frequency
PHYTxClk period
160
–
ns
160
–
ns
2.5
25
400
–
MHz
ns
40
PHYTxClk input high time
35% of nominal period
ns
PHYTxClk input low time
35% of nominal period
–
ns
PHYRxClk input frequency
PHYRxClk period
2.5
25
400
–
MHz
ns
40
PHYRxClk input high time
PHYRxClk input low time
35% of nominal period
ns
35% of nominal period
–
ns
PerClk output frequency
–
66.66
–
MHz
ns
PerClk period
15
PerClk output high time
45% of nominal period 55% of nominal period
45% of nominal period 55% of nominal period
± 0.3
ns
PerClk output low time
ns
PerClk clock edge stability (phase jitter, cycle to cycle)
ns
1000/(2T
+2ns)
–
MHz
UARTSerClk input frequency (Note 3)
UARTSerClk period
OPB
2T
T
+2
–
ns
ns
OPB
+1
UARTSerClk input high time
–
OPB
T
+1
UARTSerClk input low time
TmrClk input frequency
TmrClk period
–
66.66
–
ns
MHz
ns
OPB
–
15
TmrClk input high time
TmrClk input low time
Note:
40% of nominal period 60% of nominal period
40% of nominal period 60% of nominal period
ns
ns
1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the PowerPC 405GPr Embedded Proces-
sor User’s Manual for more information.
2. In synchronous PCI mode the PCI clock is derived from SysClk and the PCIClk input pin is unused.
3. T
is the period in ns of the OPB clock. The maximum OPB clock frequency is 66.66MHz.
OPB
44
IBM [ IBM ]
