PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 9 of 10)
Signal Name
413-Ball 456-Ball
Interface Group
Page
36
RAS
R12
L17
AF24 SDRAM
RcvrInh
C25 System
U23 PCI
39
[Req]PCIGnt0
W23
34
2
B19
C16
D18
E2
A19
3
B17
3
C13
D20
H3
2
H1
T21
V20
V21
W22
3
Other
K2
3
Notes:
N24
3
1. Y5 (on the 413-ball package) and AF4 must be tied to OV or
GND. All other reserved pins should be left unconnected.
2. Reserved on 27mm package. GND on 35mm package.
P3
DD
1
Reserved
41
Y5
3
2
U25
AA8
AB5
W26
Y23
Y26
3. Reserved on 27mm package. OV on 35mm package.
DD
1
AF4
AF8
2
3
AD14
3
AE10
SysClk
SysErr
SysReset
TCK
H16
P14
J15
U16
U13
T13
E20
L16
U17
T7
A25 System
AD25 System
D22 System
AD22 JTAG
AE24 JTAG
AD23 JTAG
D26 System
D24 System
AC22 JTAG
AB3 System
AE26 JTAG
39
39
39
39
39
39
39
39
39
39
39
TDI
TDO
TestEn
TmrClk
TMS
[TrcClk]GPIO9
TRST
T16
[TS1E]GPIO1
[TS2E]GPIO2
[TS1O]GPIO3
[TS2O]GPIO4
[TS3]GPIO5
[TS4]GPIO6
[TS5]GPIO7
[TS6]GPIO8
A20
C19
A21
AB18
AC4
AB4
AC3
Y6
D18
C20
A22
AF18
Trace
AC9
AE8
AF5
AC7
40
UART0_CTS
U7
AA17
P10
T8
AB4 Internal Peripheral
AE18 Internal Peripheral
AE3 Internal Peripheral
AF2 Internal Peripheral
AD15 Internal Peripheral
AD16 Internal Peripheral
AE16 Internal Peripheral
AF3 Internal Peripheral
AC3 Internal Peripheral
AC3 Internal Peripheral
AD2 Internal Peripheral
38
38
38
38
38
38
38
38
38
38
38
UART0_DCD
UART0_DSR
UART0_DTR
UART0_RI
AC16
AB15
AA14
U8
UART0_RTS
UART0_Rx
UART0_Tx
UART1_CTS/UART1_DSR
UART1_DSR/UART1_CTS
UART1_DTR/UART1_RTS
N8
N8
N7
Page 24 of 60
6/20/03
IBM [ IBM ]
