PowerPC 405CR Embedded Processor Data Sheet
Strapping
When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is
read to enable default initial conditions prior to PPC405CR start-up. The actual capture instant is the nearest
SysClk edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or
pull-down (logical 0) resistors to select the desired default conditions. The recommended pull-up is 3kΩ to
+3.3V or 10kΩ to +5V. The recommended pull-down is 1KΩ to GND. These pins are use for strap functions
only during reset. They are used for other signals during normal operation. The following table lists the
strapping pins along with their functions and strapping options. The signal names assigned to the pins for
normal operation follow the pin number.
Strapping Pin Assignments (Part 1 of 2)
Function
Option
Ball Strapping
U13
PLL Tuning1
W15
V20
UART0_Tx
UART0_DTR UART0_RTS
for 6 ≤ M ≤ 7 use choice 3
for 7 < M ≤ 12 use choice 5
Choice 1; TUNE[5:0] = 010001
Choice 2; TUNE[5:0] = 010010
Choice 3; TUNE[5:0] = 010011
Choice 4; TUNE[5:0] = 010100
Choice 5; TUNE[5:0] = 010101
Choice 6; TUNE[5:0] = 010110
Choice 7; TUNE[5:0] = 010111
Choice 8; TUNE[5:0] = 100100
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
for 12 < M ≤ 32 use choice 6
See Note.
PLL Forward Divider2
PLL Feedback Divider2
PLB Divider from CPU2, 3
OPB Divider from PLB2
C16
DMAAck0
B17
DMAAck1
Bypass mode
Divide by 3
Divide by 4
Divide by 6
0
0
1
1
0
1
0
1
B16
DMAAck2
A14
DMAAck3
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
0
0
1
1
0
1
1
B18
D16
GPIO1[TS1E] GPIO2[TS2E]
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
0
1
1
0
1
0
1
T4
HoldAck
U5
ExtAck
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
0
1
1
0
1
0
1
40
6/18/03
IBM [ IBM ]
