PowerPC 405CR Embedded Processor Data Sheet
Signal Descriptions
The PPC405CR embedded controller is packaged in a 316-ball enhanced plastic ball grid array (E-PBGA).
The following table provides a summary of the number of package pins associated with each functional
interface group.
Pin Summary
Group
No. of Pins
SDRAM
71
97
9
External Peripheral
External Master
Internal Peripheral
Interrupts
15
7
JTAG
5
System
18
222
1
Total Signal Pins
AVDD
OVDD
VDD
16
16
40
16
5
Gnd
Thermal (and Gnd)
Reserved
Total Pins
316
Multiplexed Pins
In the table “Signal Functional Description” on page 23, each I/O signal is listed along with a short description
of the signal function. Some signals are multiplexed onto the same package pin (ball) so that the pin can be
used for different functions. Multiplexed signals are shown as a default signal with a secondary signal in
square brackets (for example, GPIO1[TS1E]). Active-low signals (for example, RAS) are marked with an
overline.
It is expected that in any single application a particular pin will always be programmed to serve the same
function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise
be possible.
In addition to multiplexing, many pins are also multi-purpose. For example, the EBC peripheral controller
address pins are used as outputs by the PPC405CR to broadcast an address to external slave devices when
the PPC405CR has control of the external bus. When during the course of normal chip operation an external
master gains ownership of the external bus, these same pins are used as inputs which are driven by the
external master and received by the EBC in the PPC405CR.
Intialization Strapping
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs
only during reset and are used for other functions during normal operation (see “Strapping” on page 40). Note
that these are not multiplexed pins since the function of the pins is not programmable.
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6/18/03
IBM [ IBM ]
