Advance Information
TM
PowerNP NPe405L Embedded Processor Data Sheet
IIC Bus Interface
2
• Compliant with Phillips® Semiconductors I C Specification, dated 1995
• Operation at 100kHz or 400kHz
• 8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Supports fixed V IIC interface
DD
• Two independent 4 x 1 byte data buffers
• Twelve memory-mapped, fully programmable configuration registers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocol
• Programmable error recovery
HDLCEX Interface
• Multichannel HDLC controller core
• Two full-duplex Pulse Code Modulation (PCM) Highway ports at speeds up to 8 Mbps
• 32 transmit and 32 receive channels
• Supports HDLC protocol as well as a Transparent mode
• One channel per port, autonomous management of the I-Frame and S-Frame of the Normal Response
mode (NRM) protocol
• Software emulation of NRM mode
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IBM [ IBM ]
