Preliminary
PowerNP NPe405H Embedded Processor Data Sheet
NPe405H Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
x2
Clock
Control
Reset
Timers
MMU
Power
Mgmt
DCRs
See Peripheral Interface
Clock Timing table
PPC405
Processor Core
JTAG
8KB
D-Cache
DCU
Trace
ICU
DCR Bus
GPIO
x2
IIC IEC
UART
x2
16KB
I-Cache
Arb
On-chip Peripheral Bus (OPB)
DMA
Controller
(4-Channel)
OPB
Bridge
Processor Local Bus (PLB)
Ethernet
x4
MAL0
MAL1
SDRAM
Controller
13-bit addr
32-bit data
External
Bus
Controller
External
Bus Master
Controller
PCI Bridge
HDLCEX
MAL2
HDLCMP
ZMII
32-bit addr
32-bit data
66 MHz max (async)
Two
32-channel
ports
8
MII, RMII,
single-channel
ports
SMII
The NPe405H is designed using the IBM Microelectronics Blue Logic
methodology in which major
functional blocks are integrated to create an application-specific ASIC product. This approach provides a
consistent way to generate complex ASICs using IBM CoreConnect
Bus Architecture.
Address Map Support
The NPe405H incorporates two separate address maps. The first is a fixed processor address map that
serves the PowerPC family of processors. This address map defines the possible contents of various address
regions which the processor can access. The second address map is for Device Configuration Registers
(DCRs). The DCRs are accessed by software running on the NPe405H processor through the use of
mtdcr
and
mfdcr
commands.
5
IBM [ IBM ]
