PowerPC 740 and PowerPC 750 Embedded Microprocessor
IBM CMOS 0.20 um Copper Technology EMPPC740L and EMPPC750L
PLL Power Supply Filtering
The AVDD and L2AVDD power signals are provided on the 750 to provide power to the clock generation phase-
locked loop and L2 cache delay-locked loop respectively. To ensure stability of the internal clock, the power
supplied to the AVDD input signal should be filtered using a circuit similar to the one shown in Figure 18. The
circuit should be placed as close as possible to the AVDD pin to ensure it filters out as much noise as possible.
An identical but separate circuit should be placed as close as possible to the L2AVDD pin.
Figure 18. PLL Power Supply Filter Circuit
10 Ω
VDD
AVDD (or L2AVDD)
10µF
0.1µF
GND
Decoupling Recommendations
Due to the dynamic power management of the 750, which features large address and data buses, as well as
high operating frequencies, the 750 can generate transient power surges and high frequency noise in its
power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the 750750 system, and the 750 itself requires a clean, tightly regulated source of
power. Therefore, it is strongly recommended that the system designer place at least one decoupling capaci-
tor with a low ESR (effective series resistance) rating at each VDD and OVDD pin (and L2OVDD for the 360
CBGA) of the 750. It is also recommended that these decoupling capacitors receive their power from sepa-
rate VDD, OVDD and GND power planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should range in value from 220pF to 10µF to provide both high and low- frequency filtering,
and should be placed as close as possible to their associated VDD or OVDD pins. Suggested values for the VDD
pins – 220pF (ceramic), 0.01µF (ceramic), and 0.1µf (ceramic). Suggested values for the OVDD pins – 0.01µF
(ceramic), 0.1µf (ceramic), and 10µF (tantalum). Only SMT (surface-mount technology) capacitors should be
used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feed-
ing the VDD and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors
should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary.
They should also be connected to the power and ground planes through two vias to minimize inductance.
Suggested bulk capacitors – 100µF (AVX TPS tantalum) or 330µF (AVX TPS tantalum).
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to VDD. Unused active high inputs should be connected to GND.
All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, OVDD, and GND, pins of the 750.
Page 36
Version 1.51
PowerPC 740 and PowerPC 750 Datasheet
5/20/99
IBM [ IBM ]
