PowerPC 740 and PowerPC 750 Embedded Microprocessor
IBM CMOS 0.20 um Copper Technology EMPPC740L and EMPPC750L
Pinout Listing for the 360 CBGA package (cont.)
Signal Name
RSRV
SMI
Pin Number
Active
Low
Low
Low
—
I/O
Output
Input
Input
Input
Input
Input
I/O
D3
A12
SRESET
SYSCLK
TA
E10
H9
F1
Low
High
Low
High
High
High
Low
Low
High
Low
Low
High
High
Low
—
TBEN
TBST
A2
A11
TCK
B10
Input
Input
Output
Input
Input
Input
Input
I/O
TDI
B7
TDO
D9
TEA
J1
TLBISYNC
TMS
A3
C8
TRST
TS
A10
K7
TSIZ0-TSIZ2
TT0-TT4
WT
A9, B9, C9
Output
I/O
C10, D11, B12, C12, F11
C3
Output
—
2
G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12
VDD
3
K13
High
Output
VOLTDET
Note:
1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
2. OVDD inputs supply power to the I/O drivers and VDD inputs supply power to the processor core.
3. Internally tied to L2OVDD in the 750 360 CBGA package. This is NOT a supply pin.
4. These pins are reserved for potential future use as additional L2 address pins.
5. L2_TSTCLK may be tied to ground for normal machine operation, if extra 60x bus output hold is required on all 60x bus signals. See Table “60X Bus
Output AC Timing Specifications for the 7501,” on page 14, spec 15.
6. These pins are no connects on dd2.x and have no function. They will be added to dd3.x to select voltage levels for the L2 bus (A19) and the rest of the
I/O (W01). Leaving the pin unconnected will select the normal supply value. Connecting these pins to HRESET# or ground on dd3.x will select lower
voltage supply ranges.
5/20/99
Version 1.51
PowerPC 740 and PowerPC 750 Datasheet
Page 31
IBM [ IBM ]
