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IBM25EMPPC750LEBF4660 参数 Datasheet PDF下载

IBM25EMPPC750LEBF4660图片预览
型号: IBM25EMPPC750LEBF4660
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 466MHz, CMOS, CBGA360, 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360]
分类和应用: 时钟外围集成电路
文件页数/大小: 50 页 / 600 K
品牌: IBM [ IBM ]
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PowerPC 740 and PowerPC 750 Embedded Microprocessor  
IBM CMOS 0.20 um Copper Technology EMPPC740L and EMPPC750L  
L2 Bus Input AC Specifications  
The L2 bus input interface AC timing specifications are found in the following table. See Figure 7.  
L2 Bus Input Interface AC Timing Specifications  
See Table “Recommended Operating Conditions,” on page 7, for operating conditions.  
Num  
29,30  
24  
Characteristic  
L2SYNC_IN rise and fall time  
Min  
Max  
1.0  
Unit  
ns  
Notes  
2,3  
1
Data and parity input setup to L2SYNC_IN, 300, 333, 366  
MHz processor sorts.  
1.5  
ns  
24  
24  
25  
Data and parity input setup to L2SYNC_IN, 400 MHz pro-  
cessor sort.  
1.4  
1.1  
0.5  
ns  
ns  
ns  
1
1
1
Data and parity input setup to L2SYNC_IN, 466 MHz pro-  
cessor sort.  
L2SYNC_IN to data and parity input hold  
Note:  
1. All input specifications are measured from the midpoint voltage (1.4V) of the signal in question to the midpoint voltage of the rising edge of the input  
L2SYNC_IN. Input timings are measured at the pins (see Figure 7).  
2. Rise and fall times for the L2SYNC_IN input are measured from 0.4 to 2.4V.  
3. Guaranteed by design and characterization, and not tested.  
Figure 7. L2 Bus Input Timing Diagrams  
29  
30  
L2SYNC_IN  
VM  
24  
25  
VM  
VM  
ALL INPUTS  
VM = Midpoint Voltage (1.4V)  
Page 18  
Version 1.51  
PowerPC 740 and PowerPC 750 Datasheet  
5/20/99