PowerPC 740 and PowerPC 750 Embedded Microprocessor
IBM CMOS 0.20 um Copper Technology EMPPC740L and EMPPC750L
System Design Information
This section provides electrical and thermal design recommendations for successful application of the 750.
PLL Configuration
The 750 PLL is configured by the PLL_CFG[0-3-] signals. For a given SYSCLK (bus) frequency, the PLL con-
figuration signals set the internal CPU and VCO frequency of operation.
750 Microprocessor PLL Configuration
5
PLL_CFG
(0:3)
Processor to Bus Frequency Ratio
VCO Divider
bin
dec
0
1
0000
n/a
Rsv
0001
0010
0011
1
2
3
7.5x
7x
2
2
3
n/a
PLL Bypass
7
0100
4
2
2x
0101
0110
5
6
6.5x
2
2
6,7
2.5x
0111
1000
1001
1010
1011
1100
1101
1110
1111
7
4.5x
3x
2
2
8
9
5.5x
4x
2
10
11
12
13
14
15
2
5x
2
8x
2
6x
2
3.5x
2
4
n/a
Off
Note:
1. Reserved settings.
2. SYSCLK min is limited by the lowest frequency that manufacturing will support, see Section , “Clock AC Specifications,” for valid SYSCLK and VCO
frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode
operation. This mode is intended for factory use only. Note: The AC timing specifications given in the document do not apply in PLL-bypass mode.
4. In Clock - off mode, no clocking occurs inside the 750 regardless of the SYSCLK input.
5. The VCO to core clock ratio is 2x for 740/750. This simplifies clock frequency calculations so the user can disregard the VCO frequency. The VCO will
operate correctly when the core clock is within specification.
6. 0110 will change from 2.5x in dd2.x to 10x in dd3.x.
7. These values are for dd2.x only. In dd3.x, these PLL.CFG settings may change.
5/20/99
Version 1.51
PowerPC 740 and PowerPC 750 Datasheet
Page 35
IBM [ IBM ]
