•· System unit
-- Executes CR logical instructions and miscellaneous system instructions
-- Special register transfer instructions
•· Cache structure
-- 32K, 32-byte line, 8-way set associative instruction cache
-- 32K, 32-byte line, 8-way set associative data cache
-- Single-cycle cache access
-- Pseudo-LRU replacement
-- Copy-back or write-through data cache (on a page per page basis)
-- Supports all PowerPC memory coherency modes
-- Non-blocking instruction and data cache (one outstanding miss under hits)
-- No snooping of instruction cache
•· Memory management unit
-- 128 entry, 2-way set associative instruction TLB
-- 128 entry, 2-way set associative data TLB
-- Hardware reload for TLB's
-- 4 instruction BAT's and 4 data BATs
-- Virtual memory support for up to 4 exabytes (2
52
) virtual memory
-- Real memory support for up to 4 gigabytes (2
32
) of physical memory
•· Level 2 (L2) cache interface (not included on the PPC740)
-- Internal L2 cache controller and 4K-entry tags; external data SRAMs
-- 256K, 512K, and 1 Mbyte 2-way set associative L2 cache support
-- Copy-back or write-through data cache (on a page basis, or for all L2)
-- 64-byte(256K/512K) and 128-byte (l-Mbyte) sectored line size
-- Supports flow-through (reg-buf) synchronous burst SRAMs, pipelined
(reg-reg) synchronous burst SRAMs, and pipelined (reg-reg) late-write
synchronous burst SRAMs
-- Design supports Core-to-L2 frequency divisors of
÷1, ÷1.5, ÷2, ÷2.5,
and
÷3.
However, this specification supports the L2 frequency range specified in
supported in this document, please contact your IBM marketing representative.
•· Bus interface
-- Compatible with 60x processor interface
-- 32-bit address bus
-- 64-bit data bus
-- Bus-to-core frequency multipliers of 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x,
7x,7.5x, and 8x supported
•· Integrated power management
-- Low-power 2.6/3.3-volt design
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PPC740 and PPC750 Hardware Specifications
Preliminary and subject to change without notice
IBM [ IBM ]
