-- Three static power saving modes: doze, nap, and sleep
-- Automatic dynamic power reduction when internal functional units are idle
•· Integrated Thermal Management Assist Unit
-- On-chip thermal sensor and control logic
-- Thermal Management Interrupt for software regulation of junction
temperature
•· Testability
-- LSSD scan design
-- JTAG interface
•· Reliability and serviceability--Parity checking on 60x and L2 cache buses
3.0 General Parameters
The following list provides a summary of the general parameters of the PPC740 and
PPC750:
Technology
Die Size
Transistor count
Logic design
Packages
0.25
µm
CMOS, five-layer metal
7.56 mm x 8.79 mm (67 mm
2
)
6.35 million
Fully-static
PPC740: Surface mount 255-lead ceramic ball grid array
(CBGA) without L2 interface.
PPC750: Surface mount 360-lead ceramic ball grid array
(CBGA) with L2 interface.
2.6
Core power supply
I/O power supply
±
100mV dc
±
5% V dc
3.3 V
3.1 Electrical and Thermal Characteristics
This section provides both AC and DC electrical specifications and thermal characteris-
tics for the PPC740 and PPC750.
3.1.1 DC Electrical Characteristics
The tables in this section describe the PPC740’s and PPC750’s DC electrical character-
istics. Table 1 provides the absolute maximum ratings.
Table 1. Absolute Maximum Ratings
Characteristic
Core supply voltage
PLL supply voltage
Symbol
Vdd
AVdd
Value
-0.3 to 2.75
-0.3 to 2.75
Unit
V
V
PPC740 and PPC750 Hardware Specifications
5 of 44
Preliminary and subject to change without notice
IBM [ IBM ]
