Table 15. Pinout Listing for the 360 CBGA package (Continued)
Signal Name Pin Number Active
I/O
QREQ
RSRV
SMI
J3
Low
Low
Low
Low
—
Output
Output
Input
Input
Input
Input
Input
I/O
D3
A12
E10
H9
SRESET
SYSCLK
TA
F1
Low
High
Low
High
High
High
Low
Low
High
Low
Low
High
High
Low
—
TBEN
TBST
TCK
A2
A11
B10
B7
Input
Input
Output
Input
Input
Input
Input
I/O
TDI
TDO
D9
TEA
J1
TLBISYNC
TMS
A3
C8
TRST
TS
A10
K7
TSIZ0-TSIZ2
TT0-TT4
WT
A9, B9, C9
Output
I/O
C10, D11, B12, C12, F11
C3
Output
—
2
G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10,
N12
VDD
3
K13
High
Output
VOLTDET
Notes:
1. These are test signals for factory use only and must be pulled up to OVdd for normal machine opera-
tion.
2. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core.
3. Internally tied to L2OVDD in the PID-8t PPC750 360 CBGA package to indicate to the power supply
that a 2.5v core voltage processor is present. Future lower core voltage processors may tie this pin
internally to GND. CAUTION: this is different from the 255 CBGA package. This is NOT a supply pin.
4. These pins are reserved for potential future use as additional L2 address pins.
PPC740 and PPC750 Hardware Specifications
26 of 43
Preliminary and subject to change without notice
IBM [ IBM ]
