• Programmable timings and address
mapping
• CAS before RAS refresh
• ECC support across data and address
• Supports hardware coherency relative
to PCI access of local memory
• Page Mode accesses
• 66 MHz memory bus frequency
• 72-bit memory interface with ECC
• Self-refresh mode support
ROM/External Peripheral
• Supports ROM, Flash ROM, SRAM, and
Peripherals
• Burst and non-burst devices
• 1-5 banks (shared with SDRAM)
• 8-, 16-, 32-, and 64-bit data bus widths
• Programmable timing and address
mapping
• Shared address/data/control with
SDRAM interface
• External latch control for shared
address bus support
• Peripheral device pacing with external
“Ready”
PCI Interface
• PCI 2.1 compliant
• 32-bit PCI address/data bus
• Supports 25 to 66 MHz PCI bus speeds
• Supports processor access to all PCI
address spaces
• Error tracking/status
• Support for synchronous and asynchro-
nous clocking
• Internal PCI arbitration
• Support for fair external arbitration
Interrupt Controller
• Supports twelve (12) external interrupts
• Option for prioritized interrupt handler
vector generation
UART (2)
• Compatible with the NS 16550
• 16-byte send FIFO, 16-byte receive FIFO
• Programmable baud rate generator
• Supports 5- to 8-bit word size, 1 or 2 stop
bits, even/odd/no parity
I C (2)
• 100 and 400 KHz operation
• 8-bit data transfers
• 7- and 10-bit address decode/generation
• Master/slave capability
General Purpose Timers
• 32-bit time base, based on system clock
• Five capture event timers
• Five compare timers
JTAG
IEEE 1149.1 (JTAG) boundary scan is
included to facilitate board level testing
2
© International Business Machines Corporation1998
All Rights Reserved
Printed in the United States of America 7-98
CPC700, IBM, IBM Logo, and PowerPC are
trademarks of International Business Machines
Corporation in the United States and/or other
countries.
Other company, product, and service names may
be trademarks or service marks of others.
The information contained in this document is
subject to change without notice. The products
described in this document are NOT intended for
use in implantation or other life support applications
where malfunction may result in injury or death to
persons. The information contained in this
document does not affect or change IBM’s product
specifications or warranties. Nothing in this
document shall operate as an express or implied
license or indemnity under the intellectual property
rights of IBM or third parties. All the information
contained in this document was obtained in specific
environments, and is presented as an illustration.
The results obtained in other operating environ-
ments may vary.
T EI F R A I NC N A N DI T I
H NOMTO OTIE N HS
DOCUMENT IS PROVIDED ON AN AS IS BASIS.
I n e e tw l I Mb l a l f ra yd m e
n o v n i l B e i b e o n a as
g
a i i d r c l o i d r c l f o a yu eo t e
rsniety r niety rm ns f h
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i f r a i nc n a n di t i d ce t
n o m t o o t i e n h s om n .
u
IBM Microelectronics Division
1580 Route 52, Bldg. 504
Hopewell Junction, NY
12533-6351
The IBM home page can be found at:
http://www.ibm.com
The IBM Microelectronics Division home page
can be found at:
http://www.chips.ibm.com
CPC700 Companion Chip Specifications
Technology
Power
Supply
Range
0.35µm (0.27µm L
eff
) CMOS
3.3V +/- 5%
-40°C to 105°C
474-pin CBGA
Temperature
Packaging
*07GK21026700*
GK21-0267-00
G
IBM [ IBM ]
