CPC700 Memory Controller and PCI Bridge
High-performance companion chip for PowerPC 60x and 7xx processors
Overview
The CPC700
TM
Memory Controller and
PCI Bridge brings high-performance,
real-time control to PowerPC 60x/7xx
driven designs. This single-chip micro-
processor companion is specifically
designed for embedded systems to
provide a general purpose bridge to any
PCI bus. The CPC700 companion chip
also includes a high-speed memory
controller, internal peripherals, and
control for external ROM and external
peripherals.
This CPC700 companion chip can
function as a host bridge, as the basis for
an intelligent add-in PCI controller, or in
stand-alone modes. This versatility and
the following features can help lower
costs, enhance board efficiency and
reduce your time-to-market.
General
• Extensive programmability
• Flexible and programmable
error handling
Processor Interface
The PowerPC
TM
processor bus interface
includes the interface to the system
memory controller, as well as the
Processor Local Bus (PLB) master/slave
interface.
• 1 level processor address pipelining
• Processor bus arbiter
• L1 cache coherency support
• Two 32-byte write buffers
• Provides error tracking/status
• lwarx/stwx support (reservation cancel-
ling snoops)
• Supports Address Only cycle
Memory Controller
This memory controller provides the
local PowerPC processor with a low-
latency access path supporting external
peripherals and 5 banks of local memory.
SDRAM
• Up to 4 banks
•1
1x9 to 13x1 addressing (for 2 and 4
1
internal bank SDRAMs)
• 8 MB to 512 MB per bank
Data
Addr.
Control
ECC
8-Bi t
Data
Addr. Control
64-Bi t
32-Bi t
32 or 64-Bi t
13-Bi t
• 66 MHz SDRAM interface
• External peripheral bus
• PCI 2. compliant interface
1
(32-bit, 25 to 66 MHz)
• Supports internal or external PCI
bus arbitration
• Interrupt controller
• Programmable timers
• Two full-duplex UARTs (16550)
• Two I
2
C interfaces
• Byte swapping options ease
communication in little-endian systems
• JTAG for board-level testing
Memory Controller
Processor Interface
64-Bi t
(SDRAM, ROM,
Peripherals)
33 MHz On-Chip Peripheral Bus (OPB)
• PowerPC 60x/7xx interface (66 MHz)
UART
UART
I 2
C
I 2
C
32-Bi t
66 MHz Processor Local Bus (PLB)
32-Bi t
OPB
Bridge
PCI Interface
32-Bi t
Interrupt
Controller
Timers
JTAG
Data/Address
Control
CPC700 Block Diagram
IBM [ IBM ]
