Discontinued (8/99 - last order; 12/99 - last ship)
IBM13N16644HC
IBM13N16734HC
16M x 64/72 2 Bank Unbuffered SDRAM Module
AC Characteristics (T = 0 to +70°C, V = 3.3V ± 0.3V)
A
DD
An initial pause of 200µs, with DQMB0-7 and CKE0-CKE1 held high, is required after power-up. A Precharge All Banks
command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set
operation.
1. The Transition time is measured between VIH and VIL (or between VIL and VIH).
2. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
3. Load Circuit A: AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V crossover point
4. Load Circuit A: AC measurements assume tT=1.0 ns.
5. Load Circuit B: AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V crossover point
6. Load Circuit B: AC measurements assume tT=1.2 ns.
AC Characteristics Diagrams
t
T
t
CKH
Vtt=1.4V
VIH
1.4V
VIL
Clock
Input
50Ω
t
CKL
Output
Z = 50Ω
o
50pF
50pF
t
SETUP
t
HOLD
AC Output Load Circuit (A)
1.4V
Output
t
OH
Z = 50Ω
o
t
AC
t
LZ
AC Output Load Circuit (B)
Output
1.4V
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L7123.E93760A
2/99
Page 12 of 18
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