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IBM11S2325HM-6RT 参数 Datasheet PDF下载

IBM11S2325HM-6RT图片预览
型号: IBM11S2325HM-6RT
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM Module, 2MX32, 60ns, CMOS]
分类和应用: 动态存储器内存集成电路
文件页数/大小: 22 页 / 213 K
品牌: IBM [ IBM ]
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IBM11S2325HP IBM11S4325HP
IBM11S2325HM IBM11S4325HM
2M/4M x 32 SO DIMM Module
Extended Data Out Cycle
Symbol
t
HCAS
t
HPC
t
DOH
t
WHZ
t
WPZ
t
CPRH
t
CPA
t
RASP
Parameter
CAS Pulse Width (EDO Mode)
EDO Mode Cycle Time (Read/Write)
Data-out Hold Time from CAS
Output buffer Turn-Off Delay from WE
WE Pulse Width to Output Disable at CAS High
RAS Hold Time from CAS Precharge
Access Time from CAS Precharge
EDO Mode RAS Pulse Width
-60
-6R
-70
Units
Min. Max. Min. Max. Min. Max.
10 10K 10 10K 12 10K
ns
25
5
0
10
35
60
10
35
125K
25
5
0
10
35
60
10
35
125K
30
5
0
10
40
70
15
40
125K
ns
ns
ns
ns
ns
ns
ns
1
Notes
1. Measured with the specified current load and 100pF at V
OL
= 0.8V and V
OH
= 2.0V.
Refresh Cycle
Symbol
t
CHR
t
CSR
t
WRP
t
WRH
t
RPC
t
REF
Parameter
CAS Hold Time
(CAS before RAS Refresh Cycle)
CAS Setup Time
(CAS before RAS Refresh Cycle)
WE Setup Time
(CAS before RAS Refresh Cycle)
WE Hold Time
(CAS before RAS Refresh Cycle)
RAS Precharge to CAS Hold Time
Refresh Period
-60
Min
10
5
10
10
5
Max
128
Min
10
5
10
10
5
-6R
Max
128
Min
10
5
10
10
5
-70
Max
128
Units
ns
ns
ns
ns
ns
ms
1
Notes
1. 2048 refreshes are required every 128ms.
Self Refresh Cycle
Symbol
Parameter
RAS Pulse Width
During Self Refresh Cycle
RAS Precharge Time
During Self Refresh Cycle
CAS Hold Time
During Self Refresh Cycle
CAS Hold Time From RAS Falling
During Self Refresh Cycle
-60
Min.
100
104
-50
350
Max.
Min.
100
110
-50
350
-6R
Max.
Min.
100
126
-50
350
-70
Max.
Units
µs
ns
ns
µs
Notes
1
1
1, 2
1, 2
t
RASS
t
RPS
t
CHS
t
CHD
1. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row
addresses are being refreshed in a EVENLY DISTRIBUTED manner over the refresh interval using CBR refresh cycles, then only
one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other
manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed imme-
diately before entry to and immediately after exit from Self Refresh.
2. If t
RASS
> t
CHD
(min) then t
CHD
applies. If t
RASS
t
CHD
(min) then t
CHS
applies.
75H1718
SA14-4471-00
Revised 4/96
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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