IBM11M8735C
IBM11M8735CB
8M x 72 DRAM MODULE
Read Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRCD
tRSH
tCRP
VIH
CAS
tCAS
VIL
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH
VIL
Address
Row
Column
tRCH
tRRH
tWRP
tWRH
tRCS
VIH
VIL
NOTE 1
WE
OE
tAA
tOES
VIH
VIL
tOEA
tDZC
tCDD
tDZO
tODD
VIH
VIL
DIN
Hi-Z
tCAC
tCLZ
tOFF
tOEZ
VOH
VOL
DOUT
Hi-Z
Valid Data Out
Hi-Z
tRAC
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H”: or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H8010
SA14-4635-02
Revised 5/96
Page 12 of 29
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