Discontinued (9/98 - last order; 3/99 last ship)
IBM11M1645L
1M x 64 DRAM MODULE
Truth Table
Function
Standby
Read
Early-Write
Late-Write
RMW
EDO Page Mode - Read
1st Cycle
Subsequent Cycles
EDO Page Mode - Write
1st Cycle
Subsequent Cycles
EDO Page Mode - RMW
1st Cycle
Subsequent Cycles
RAS-Only Refresh
CAS-Before-RAS Refresh
Hidden Refresh
Read
Write
Read Presence Detects
RAS
H
L
L
L
L
L
L
L
L
L
L
L
H→L
L→H→L
L→H→L
X
CAS
H→X
L
L
L
L
H→L
H→L
H→L
H→L
H→L
H→L
H
L
L
L
X
WE
X
H
L
H→L
H→L
H
H
L
L
H→L
H→L
X
H
H
H
X
OE
X
L
X
H
L→H
L
L
X
X
L→H
L→H
X
X
L
X
X
Row
Address
X
Row
Row
Row
Row
Row
N/A
Row
N/A
Row
N/A
Row
X
Row
Row
X
Column
Address
X
Col
Col
Col
Col
Col
Col
Col
Col
Col
Col
N/A
X
Col
Col
X
PDE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
DQx
High Impedance
Valid Data Out
Valid Data In
Valid Data In
Valid Data Out,
Valid Data In
Valid Data Out
Valid Data Out
Valid Data In
Valid Data In
Valid Data Out,
Valid Data In
Valid Data Out,
Valid Data In
High Impedance
High Impedance
Data Out
Data In
Not Affected
(PD Bits Valid)
Presence Detect
Pin
PD1 (PD1 - PD4: Addressing/Density)
PD2
PD3
PD4
PD5 (EDO Detection)
PD6 (PD6 - PD7: Speed)
PD7
PD8 (Parity/ECC Designator)
ID0 (DIMM Type/Width)
ID1 (Refresh Mode)
1. PD1-8 are buffered outputs (0 = driven to V
OL
, 1 = open)
2. ID0-1 are unbuffered outputs (0 = V
SS
, 1 = open)
3. PDE should be tied high or low at system level if not used
-60
0
0
1
0
1
1
1
1
0
0
-70
0
0
1
0
1
0
1
1
0
0
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4196
SA14-4617-04
Revised 12/96
Page 4 of 29
IBM [ IBM ]
