欢迎访问ic37.com |
会员登录 免费注册
发布采购

IBM0612805GT3B-75N 参数 Datasheet PDF下载

IBM0612805GT3B-75N图片预览
型号: IBM0612805GT3B-75N
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 16MX8, 0.75ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66]
分类和应用: 动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 79 页 / 1362 K
品牌: IBM [ IBM ]
 浏览型号IBM0612805GT3B-75N的Datasheet PDF文件第48页浏览型号IBM0612805GT3B-75N的Datasheet PDF文件第49页浏览型号IBM0612805GT3B-75N的Datasheet PDF文件第50页浏览型号IBM0612805GT3B-75N的Datasheet PDF文件第51页浏览型号IBM0612805GT3B-75N的Datasheet PDF文件第53页浏览型号IBM0612805GT3B-75N的Datasheet PDF文件第54页浏览型号IBM0612805GT3B-75N的Datasheet PDF文件第55页浏览型号IBM0612805GT3B-75N的Datasheet PDF文件第56页  
IBM0612404GT3B  
IBM0612804GT3B  
128Mb Double Data Rate Synchronous DRAM  
Advance Rev 0.2  
Capacitance  
Parameter  
Input Capacitance: CK, CK  
Symbol  
CI  
Min.  
2.5  
Max.  
3.5  
Units  
pF  
Notes  
1
1
1
Delta Input Capacitance: CK, CK  
delta CI  
0.25  
3.0  
pF  
1
Input Capacitance: All other input-only pins (except DM)  
Delta Input Capacitance: All other input-only pins (except DM)  
Input/Output Capacitance: DQ, DQS, DM  
Delta Input/Output Capacitance: DQ, DQS, DM  
Output Capacitance: QFC  
CI  
2.0  
4.0  
2.0  
pF  
1
2
delta CI  
0.5  
pF  
1
2
C
5.0  
pF  
1, 2  
1
IO  
delta C  
0.5  
pF  
IO  
CO  
4.0  
pF  
1
1
1. V  
= V = 2.5V 0.2V (minimum range to maximum range), f = 100MHz, T = 25°C, VO = V  
, VO  
= 0.2V.  
Peak -Peak  
DDQ  
DD  
A
DC  
DDQ/2  
2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This  
is required to match input propagation times of DQ, DQS and DM in the system.  
DC Electrical Characteristics and Operating Conditions  
(0˚C TA 70°C; VDDQ = 2.5V ± 0.2V, VDD = + 2.5V ± 0.2V, see AC Characteristics)  
Symbol  
Parameter  
Min  
2.3  
2.3  
Max  
2.7  
Units  
V
Notes  
V
Supply Voltage  
1
1
DD  
V
I/O Supply Voltage  
2.7  
V
DDQ  
Supply Voltage  
I/O Supply Voltage  
V
, V  
0
0
V
SS  
SSQ  
V
I/O Reference Voltage  
0.49 x V  
0.51 x V  
DDQ  
V
V
V
V
V
V
V
1, 2  
1, 3  
1
REF  
DDQ  
V
I/O Termination Voltage (System)  
Input High (Logic1) Voltage  
V
V
0.04  
+ 0.15  
V
+ 0.04  
REF  
TT  
REF  
REF  
V
V
+ 0.3  
DDQ  
IH(DC)  
V
Input Low (Logic0) Voltage  
0.3  
V
0.15  
REF  
1
IL(DC)  
IN(DC)  
ID(DC)  
IX(DC)  
V
V
V
Input Voltage Level, CK and CK Inputs  
Input Differential Voltage, CK and CK Inputs  
Input Crossing Point Voltage, CK and CK Inputs  
0.3  
0.30  
0.30  
V
+ 0.3  
+ 0.6  
+ 0.6  
1
DDQ  
DDQ  
DDQ  
V
1, 4  
1, 4  
V
Input Leakage Current  
I
5  
5  
5
µA  
µA  
1
1
I
Any input 0V V V ; (All other pins not under test = 0V)  
IN  
DD  
Output Leakage Current  
(DQs are disabled; 0V V V  
I
5
OZ  
out  
DDQ  
I
Output Current: Nominal Strength Driver  
16.8  
16.8  
9.0  
9.0  
OH  
High current (V  
Low current (V  
= V  
-0.373V, min V  
, min V  
)
)
mA  
mA  
1
1
OUT  
DDQ  
REF  
TT  
I
= 0.373V, max V  
, max V )  
OL  
OUT  
REF  
TT  
I
Output Current: Weak Strength Driver  
OHW  
High current (V  
Low current (V  
= V  
-0.763V, min V  
, min V  
REF  
OUT  
DDQ  
TT  
I
= 0.763V, max V  
, max V )  
OLW  
OUT  
REF  
TT  
1. Inputs are not recognized as valid until VREF stabilizes.  
2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the  
same. Peak-to-peak noise on VREF may not exceed 2% of the DC value.  
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set  
equal to VREF, and must track variations in the DC level of VREF  
.
4. VID is the magnitude of the difference between the input level on CK and the input level on CK.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
06K0566.F39350  
5/00  
Page 52 of 79  
 复制成功!