IBM0612404GT3B
IBM0612804GT3B
128Mb Double Data Rate Synchronous DRAM
Advance Rev 0.2
Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Write
NOP
NOP
NOP
Read
NOP
Command
t
WTR
BAa, COL b
BAa, COL n
Address
CL = 2
t
(max)
DQSS
DQS
DQ
DI a-b
DM
Minimum DQSS
T5 T6
T1
T2
T3
T4
CK
CK
Write
NOP
NOP
NOP
Read
NOP
Command
t
WTR
BAa, COL n
BAa, COL b
Address
CL = 2
t
(min)
DQSS
DQS
DQ
DI a-b
DM
DI a-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
A non-interrupted burst is shown.
t
is referenced from the first positive CK edge after the last data in pair.
WTR
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands may be to any bank.
Don’t Care
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
06K0566.F39350
5/00
Page 36 of 79
IBM [ IBM ]
