.
IBM0418A4ACLAB
IBM0436A8ACLAB
Preliminary
IBM0418A8ACLAB
IBM0436A4ACLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Features
• 8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
• 0.25 Micron CMOS technology
• Synchronous Register-Latch Mode of Operation
with Self-Timed Late Write
• Single Differential HSTL Clock
• +3.3V Power Supply, Ground, 2.0V max V
DDQ
,
and 0.85V V
REF
• HSTL Input and Output levels
• Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins
• Latched Outputs
• Common I/O
• Asynchronous Output Enable
• Synchronous Power Down Input
• Boundary Scan using limited set of JTAG
1149.1 functions
• Byte Write Capability & Global Write Enable
• 7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
Description
The 4 and 8Mb SRAM
S
—IBM0436A4ACLAB,
IBM0436A8ACLAB, IBM0418A4ACLAB, and
IBM0418A8ACLAB—are Synchronous Register-
Latch Mode, high-performance CMOS Static Ran-
dom Access Memories that are versatile, have wide
I/O, and can achieve 3.8 ns cycle times. Differential
K clocks are used to initiate the read/write operation
and all internal operations are self-timed. At the ris-
ing edge of the K clock, all Addresses, Write-
Enables, Sync Select, and Data Ins are registered
internally. Data Outs are updated from output regis-
ters off the falling edge of the K clock. An internal
Write buffer allows write data to follow one cycle
after addresses and controls. The chip is operated
with a single +3.3V power supply and is compatible
with HSTL I/O interface.
crlh3320.06
12/00
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