IBM0418A4ACLAB IBM0418A8ACLAB
IBM0436A8ACLAB IBM0436A4ACLAB
Preliminary
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
AC Characteristics (TA = 0 to +85°C, VDD = 3.3V -5%, +5%, VDDQ = 1.9V, Clocks run from 0.9 to 1.7V, VCM
=
1.3V, VREF = 0.85V).
-37
-43
-45
-50
-55
Parameter
Symbol
Units
Notes
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
t
Cycle Time
3.8
1.5
1.5
—
—
—
4.2
1.5
1.5
—
—
—
4.5
1.5
1.5
—
—
—
5.0
1.5
1.5
—
—
—
5.5
1.5
1.5
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
KHKH
t
t
Clock High Pulse Width
Clock Low Pulse Width
Clock High to Output Valid
Clock Low to Output Valid
Address Setup Time
KHKL
KLKH
—
—
—
—
—
1, 5, 6
1
t
3.7
1.7
—
4.2
1.9
—
4.5
2.0
—
5.0
2.25
—
5.5
2.5
—
KHQV
t
t
t
—
—
—
—
—
KLQV
AVKH
3, 8
3
0.3
0.8
0.3
0.8
0.3
0.8
0.3
0.8
0.7
0.7
0.8
—
0.4
0.8
0.4
0.8
0.4
0.8
0.4
0.8
0.5
0.5
1.0
—
0.5
1.0
0.5
1.0
0.5
1.0
0.5
1.0
0.5
0.5
—
0.5
1.0
0.5
1.0
0.5
1.0
0.5
1.0
0.5
0.5
—
0.5
1.0
0.5
1.0
0.5
10
Address Hold Time
—
—
—
—
—
KHAX
SVKH
KHSX
3, 8
3
t
t
Sync Select Setup Time
Sync Select Hold Time
Write Enables Setup Time
Write Enables Hold Time
Data In Setup Time
—
—
—
—
—
—
—
—
—
—
3, 8
3
t
t
—
—
—
—
—
WVKH
KHWX
—
—
—
—
—
3, 8
3
t
—
—
—
—
0.5
1.0
0.5
0.5
—
—
DVKH
t
Data In Hold Time
—
—
—
—
—
KHDX
1, 4
1, 4
1, 4, 6, 7
1, 4
1
t
Clock Low to Data Out Hold Time
Clock Low to Output Active
Clock High to Output High-Z
Output Enable to High-Z
Output Enable to Low-Z
Output Enable to Output Valid
Output Enable Setup Time
Output Enable Hold TIme
Sleep Mode Setup Time
Sleep Mode Hold Time
Sleep Mode Recovery TIme
Sleep Mode Enable TIme
—
—
—
—
—
KLQX
t
—
—
—
—
—
KLQX4
t
2.0
2.0
—
2.5
2.5
—
2.5
2.5
—
2.5
2.5
—
2.5
2.5
—
KHQZ
t
—
—
—
GHQZ
t
t
t
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
GLQX
GLQV
1
1.8
—
1.8
—
1.8
—
1.8
—
1.8
—
1, 2
1, 2
0.5
1.5
1.0
1.0
200
—
0.5
1.5
1.0
1.0
200
—
0.5
1.5
1.0
1.0
200
—
0.5
1.5
1.0
1.0
200
—
0.5
1.5
1.0
1.0
200
—
GHKH
t
—
—
—
—
—
KHGX
t
—
—
—
—
—
ZVKH
t
9
—
—
—
—
—
KHZX
t
—
—
—
—
—
ZZR
t
9.0
9.0
9.0
10.0
11.0
ZZE
1. See the AC Test Loading figure on page 12.
2. Output Driver Impedance update specifications for G induced updates. Write and Deselect cycles will also induce Output Driver
updates during High-Z.
3. During normal operation, V ,V ,T
, and T
of inputs must be within 20% of V , V , T
, and T
of Clock.
FALL
IH IL RISE
FALL
IH
IL RISE
4. Verified by design and tested without guardband ..
5. t guaranteed with 0.150 ns guardband at 3.8ns cycle time.
KHQV
6. Minimum t
and maximum t
cannot occur at the same time. Contact Applications for more details.
KHQV
KHQZ
7. t
minx spec remains at o.8ns for -37 speed sort, But parts at t
=3.7ns, are guaranteed to be at least 1.6ns.
KHQV
KHQZ
8. Verified by design and tested without guardband for -37ns speed sort.
9. For t <200ns, access time will be equal to twice t
.
KHQV
ZZR
crlh3320.06
12/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 13 of 27
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