.
Preliminary
Features
• 32Kx36 or 64Kx18 organizations
• 0.25 Micron CMOS technology
• Synchronous Pipeline Mode of Operation with
Self-Timed Late Write
• Differential PECL Clocks or 2.5V LVTTL swing
with one clock tied to V
DDQ
/2
• +3.3V Power Supply, Ground, 2.5V V
DDQ
• 2.5V LVTTL Input and Output levels
• Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins
IBM0436A11NLAA
IBM0418A11NLAA
32Kx36 & 64Kx18 SRAM
• Registered Outputs
• 30 Ohm Drivers
• Common I/O
• Asynchronous Output Enable
• Synchronous Power Down Input
• Boundary Scan using limited set of JTAG
1149.1 functions
• Byte Write Capability and Global Write Enable
• 7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
Description
IBM0436A11NLAA and IBM0418A11NLAA are 1Mb
Synchronous Pipeline Mode, high-performance
CMOS Static Random Access Memories (SRAM).
These SRAMs are versatile, have a wide input/out-
put (I/O) interface, and can achieve cycle times as
short as 3.0ns. Differential K clocks are used to ini-
tiate the read/write operation; all internal operations
are self-timed. At the rising edge of the K clock, all
address, write-enable, sync select, and data input
signals are registered internally. Data outputs are
updated from output registers off the next rising
edge of the K clock. An internal write buffer allows
write data to follow one cycle after addresses and
controls. The device is operated with a single +3.3V
power supply and is compatible with 2.5V LVTTL I/O
interfaces.
nrrL3325.00
08/06/2001
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 24
IBM [ IBM ]
