.
Advance
Features
IBM0418A8CXLBB IBM0436A8CXLBB
IBM0418A4CXLBB IBM0436A4CXLBB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
• 8Mb: 256K x 36 or 512K x 18 Organizations
• 4Mb: 128K x 36 or 256K x 18 Organizations
• CMOS Technology
• Double Data Rate and Single Data Rate Syn-
chronous Modes of Operation
• Pipeline Mode of Operation
• Self-Timed Late Write with Full Data Coherency
• Single Differential HSTL Clock
• +2.5V Power Supply, Ground, 1.6V V
DDQ
, and
0.95V V
REF
• HSTL Input and Output levels
• Registered Addresses, Controls, and Data Ins.
• Burst Mode of operation
• Common I/O
• Asynchronous Output Enable
• Boundary Scan using limited set of JTAG
1149.1 functions
• 9 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
• Programmable Impedance Output Drivers
Description
The IBM0436A4CXLBB, IBM0418A4CXLBB,
IBM0418A8CXLBB, and IBM0436A8CXLBB
SRAM
S
are Synchronous Pipeline Mode, high-per-
formance CMOS Static Random Access Memories
that are versatile, have wide I/O, and achieve 4ns
cycle times. Differential CK clocks are used to ini-
tiate the read/write operation and all internal opera-
tions are self-timed. At the rising edge of the CK
clock, all Addresses, Controls, and Data Ins are reg-
istered internally. Data Outs are updated from out-
put registers off the next rising and falling edge of
the K clock, hence the Double Data Rate. Internal
Write buffers allow write data to follow one cycle
after addresses and controls. The chip is operated
with a single +2.5V power supply and is compatible
with HSTL I/O interfaces.
tddrh2516.01
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