Preliminary
IBM0418A4ACLAB IBM0418A8ACLAB
IBM0436A8ACLAB IBM0436A4ACLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Pin Description
SA0-SA18
Address Input
SA0-SA18 for 512Kx18
SA0-SA17 for 256Kx36
SA0-SA17 for 256Kx18
SA0-SA16 for 128Kx36
Data I/O
DQ0-DQ17 for 512Kx18
DQ0-DQ35 for 256Kx36
Differential Input Register Clocks
Write Enable, Global
Write Enable, Byte a (DQ0-DQ8)
Write Enable, Byte b (DQ9-DQ17)
Write Enable, Byte c (DQ18-DQ26)
Write Enable, Byte d (DQ27-DQ35)
IEEE 1149.1 Test Inputs (LVTTL levels)
IEEE 1149.1 Test Output (LVTTL level)
G
Asynchronous Output Enable
DQ0-DQ35
SS
Synchronous Select
Clock Mode Inputs- Selects Single or Dual Clock
Operation.
HSTL Input Reference Voltage
Power Supply (+3.3V)
Ground
Output Power Supply
Asynchronous Sleep Mode
Output Driver Impedance Control
No Connect
K, K
SW
SBWa
SBWb
SBWc
SBWd
TMS,TDI,TCK
TDO
M1, M2
V
REF
(2)
V
DD
V
SS
V
DDQ
ZZ
ZQ
NC
crlh3320. 01
7/99
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Use is further subject to the provisions at the end of this document.
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