Preliminary
IBM0418A8CFLBB IBM0436A8CFLBB
IBM0418A4CFLBB IBM0436A4CFLBB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Pin Description
Address Inputs
SA0-SA1 Burst control starting addresses
SA0-SA18 for 512K x 18
SA0-SA17 for 256K x 36
SA0-SA17 for 256K x 18
SA0-SA16 for 128K x 36
Data I/O
DQ0-DQ17 for 512K x 18
DQ0-DQ35 for 256K x 36
Output Differential Echo Clocks
Differential Input Register Clocks
Synchronous Function Control Input. B1 = 0
Loads a new Address
Synchronous Function Control Input (WE). B2
= 0 starts Write & B2 = 1 starts Read.
Synchronous Function Control Input. B3 = 0
starts a DDR (Burst) operation. B3 = 1 starts a
SDR (Single Data Rate)
Linear Burst Order, (LBO =1 interleave mode,
LBO = 0 linear mode)
Asynchronous Output Enable
SA0-SA18
TMS,TDI,TCK IEEE 1149.1 Test Inputs (LVTTL levels)
DQ0-DQ35
TDO
IEEE 1149.1 Test Output (LVTTL level)
CQ, CQ
CK, CK
B1
V
REF
(2)
V
DD
V
SS
V
DDQ
Extended HSTL Input Reference Voltage
Power Supply (+2.5V)
Ground
B2
Output Power Supply
B3
ZQ
Input pin for Output Driver Impedance Control.
LBO
G
NC
No Connect
cddrh251620.07
12/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 26
IBM [ IBM ]
