IBM0418A8CBLBB IBM0436A8CBLBB
IBM0418A4CBLBB IBM0436A4CBLBB
Preliminary
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18)
AC Characteristics (TA = 0 to +85°C, VDD = 2.5V +/-5%)
-.3P
-.3
-4
-4H
-5
Parameter
Symbol
Units Notes
Min. Max.
Min. Max. Min. Max. Min. Max. Min. Max.
t
3.0
1.2
1.2
0.4
0.4
—
—
—
—
—
Cycle Time
3.5
1.5
1.5
0.5
0.5
—
—
—
—
—
4.0
1.5
1.5
0.5
0.5
—
—
—
—
—
4.5
1.5
1.5
0.5
0.5
—
—
—
—
—
5.0
2.0
2.0
0.5
0.5
—
—
—
—
—
ns
ns
ns
KHKH
t
CK Clock High Pulse Width
CK Clock Low Pulse Width
Address Setup Time
KHKL
t
KLKH
t
3
3
ns
ns
AVKH
t
Address Hold Time
KHAX
Function Control (B1, B2, B3) Setup
Time
t
0.5
0.5
—
—
3
3
0.5
0.5
—
—
0.5
0.5
—
—
0.5
0.5
—
—
0.5
0.5
—
—
ns
ns
BVKH
Function Control (B1, B2, B3) Hold
Time
t
KHBX
t
0.4
0.4
—
—
Data In Setup Time
Data In Hold Time
3
3
0.5
0.5
—
—
0.5
0.5
—
—
0.5
0.5
—
—
0.5
0.5
—
—
ns
ns
DVKH
t
KHDX
t
t
t
t
t
t
t
t
t
t
t
t
KHKL KHKL
KHKL KHKL KHKL KHKL KHKL KHKL KHKL KHKL
t
Echo Clock (CQ) High Pulse Width
Echo Clock (CQ) Low Pulse Width
ns
ns
CHCL
-0.1 +0.1
-0.1 +0.1 -0.1 +0.1 -0.1 +0.1 -0.1 +0.1
t
t
t
t
t
t
t
t
KLKH KLKH
KLKH KLKH KLKH KLKH KLKH KLKH KLKH KLKH
t
CLCH
-0.1 +0.1
-0.1 +0.1 -0.1 +0.1 -0.1 +0.1 -0.1 +0.1
Clock (CK) crossing to Echo clock (CQ)
High
t
tbd
tbd
1.7
1.7
—
—
2.0
2.0
—
—
2.0
2.0
—
—
2.25
2.25
—
—
2.5
2.5
ns
ns
KXCH
Clock (CK) crossing to Echo clock (CQ)
Low
t
KXCL
t
—
—
0.2
0.2
—
Echo clock (CQ) High to output valid
Echo clock (CQ) Low to output valid
Echo clock (CQ) High to output Hold
Echo clock (CQ) Low to output Hold
4
4
4
4
—
—
0.2
0.2
—
—
—
0.2
0.2
—
—
—
0.2
0.2
—
—
—
0.2
0.2
ns
ns
ns
ns
CHQV
t
CLQV
t
-0.2
-0.2
-0.2
-0.2
-0.2
-0.2
-0.2
-0.2
-0.2
-0.2
CHQX
t
—
—
—
—
CLQX
Echo clock (CQ) High to output High -
Z
t
—
0.2
4
—
0.2
—
0.2
—
0.2
—
0.2
ns
CHQZ
t
-0.2
—
—
2.5
—
Echo clock (CQ) High to output Low - Z
Output Enable (G) High to High - Z
Output Enable (G) Low to Low - Z
Output Enable (G) to Output Valid
Output Enable (G) Setup Time
4
1
-0.2
—
—
2.5
—
-0.2
—
—
2.5
—
-0.2
—
—
2.5
—
-0.2
—
ns
ns
ns
ns
ns
ns
CHLZ
t
3.0
—
GHQZ
t
0.5
—
1
0.5
—
0.5
—
0.5
—
0.5
—
GLQX
t
2.0
—
1
2.0
—
2.0
—
2.25
—
2.5
—
GLQV
t
0.5
1.0
1, 2
1, 2
0.5
1.0
0.5
1.0
0.5
1.0
0.5
1.0
GHKH
t
—
Output Enable (G) Hold TIme
—
—
—
—
KHGX
1. See the AC Test Loading figure on page 12.
2. Output Driver Impedance update specifications for G induced updates. Write and NOP cycles will also induce Output Driver
updates during High-Z.
3. During normal operation, V ,V ,T
, and T
of inputs must be within 20% of V , V , T
, and T
of Clock.
FALL
IH IL RISE
FALL
IH
IL RISE
4. These values will be guaranteed by design.
cddrh2519.04
12/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 13 of 26
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