IBM0418A4ACLAA IBM0418A8ACLAA
IBM0436A8ACLAA IBM0436A4ACLAA
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Read and Write Cycles Timing Diagram
t
KLKH
t
t
KHKH
KHKL
K
t
AVKH
A2
A1
A3
A2
A4
SA
SS
SW
t
KHAX
t
SVKH
t
KHSX
t
KHWX
t
KHWX
t
WVKH
t
WVKH
t
KHWX
t
KHWX
SBW
t
WVKH
t
WVKH
t
KLQV
G
t
GHQZ
t
t
KHQV
t
KHQZ
KLQX4
D4
Q3
Q2
Q1
D2
DQ
t
KHDX
t
t
DVKH
KHQV
t
DVKH
t
KHDX
Notes:
1. D2 is the input data written in memory location A2.
2. Q2 is output data read from the write buffer, as a result of address A2 being a match from the last write cycle address.
trlh3320.04
01/01
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Use is further subject to the provisions at the end of this document.
Page 14 of 26
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