IBM0418A81QLAB IBM0436A81QLAB
IBM0418A41QLAB IBM0436A41QLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
AC Characteristics (TA = 0 to +85°C, VDD = 3.3V -5%, +10%)
3P
3
3F
3N
4
5
Parameter
Symbol
Units Notes
ns
Min Max Min Max Min Max Min Max Min Max Min Max
t
Cycle Time
3.0
1.2
1.2
—
—
—
—
1.5
—
—
—
—
—
—
—
—
—
2.25
—
2.0
—
2.0
—
—
—
—
—
6
3.0
1.2
1.2
—
—
—
—
1.7
—
—
—
—
—
—
—
—
—
2.25
—
2.0
—
2.0
—
—
—
—
—
6
3.3
1.5
1.5
—
—
—
3.7
1.5
1.5
—
—
—
4.0
1.5
1.5
—
—
—
—
2.0
—
—
—
—
—
—
—
—
—
2.25
—
2.0
—
2.0
—
—
—
—
—
8
5.0
1.5
1.5
—
—
—
KHKH
t
5
5
Clock High Pulse Width
Clock Low Pulse Width
Clock to Output Valid
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
KHKL
t
—
—
—
KLKH
t
1
1.8
—
1.8
—
2.25
—
KHQV
t
3
Address Setup Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
—
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
—
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
—
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
—
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
—
0.5
1.0
0.5
1.0
0.5
1.0
0.5
1.0
0.5
—
AVKH
t
3
Address Hold Time
—
—
—
KHAX
t
3
Sync Select Setup Time
Sync Select Hold Time
Write Enables Setup Time
Write Enables Hold Time
Data In Setup Time
—
—
—
SVKH
t
3
—
—
—
KHSX
t
3
—
—
—
WVKH
t
3
—
—
—
KHWX
t
3
—
—
—
DVKH
t
3
Data In Hold Time
—
—
—
KHDX
t
1
Data Out Hold Time
—
—
—
KHQX
t
1, 4
1, 4
1, 4
1
Clock High to Output High-Z
Clock High to Output Active
Output Enable to High-Z
Output Enable to Low-Z
Output Enable to Output Valid
Output Enable Setup Time
Output Enable Hold TIme
Sleep Mode Setup Time
Sleep Mode Hold Time
Sleep Mode Recovery TIme
Sleep Mode Enable TIme
2.25
—
2.25
—
2.5
—
KHQZ
t
0.5
0.5
—
0.5
0.5
0.5
0.5
—
KHQX4
t
2.0
—
2.0
—
2.5
—
GHQZ
t
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
GLQX
t
1
2.0
—
2.0
—
2.5
—
GLQV
t
1, 2
1, 2
0.5
1.5
1.0
1.0
200
—
0.5
1.5
1.0
1.0
200
—
0.5
1.5
1.0
1.0
200
—
0.5
1.5
1.0
1.0
200
—
0.5
1.5
1.0
1.0
200
—
0.5
1.5
1.0
1.0
200
—
GHKH
t
—
—
—
KHGX
t
—
—
—
ZVKH
t
—
—
—
KHZX
t
6
—
—
—
ZZR
t
6.6
7.4
10
ZZE
1. See the AC Test Loading figure on page 11.
2. Output Driver Impedance update specifications for G induced updates. Write and Deselect cycles will also induce Output Driver
updates during High-Z.
3. During normal operation, V , V , T
, and T
of inputs must be within 20% of V , V , T
, and T
of Clock.
FALL
IH
IL RISE
FALL
IH
IL RISE
4. Verified by design and tested without guardbands.
5. Minimum pulse is guaranteed by design for -3P and -3 speed sorts.
6. For t
<200ns, access time will be equal to twice t
.
ZZR
KHQV
crrh3316.08
12/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 26
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