.
Preliminary
Features
• 32K x 36 or 64K x 18 organizations
• 0.25µ CMOS technology
• Synchronous Register-Latch Mode of Operation
with Self-Timed Late Write
• Single Differential PECL Clock
• +3.3V Power Supply, Ground, 2.5V V
DDQ
• 2.5V LVTTL Input and Output levels
• Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins
• Latched Outputs
• Common I/O
• 30Ω Drivers
IBM0418A1ANLAA
IBM0436A1ANLAA
32Kx36 & 64Kx18 SRAM
• Asynchronous Output Enable and Power Down
Inputs
• Boundary Scan using limited set of JTAG
1149.1 functions
• Byte Write Capability & Global Write Enable
• 7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
Description
IBM0436A1ANLAA and IBM0418A1ANLAA are
1Mb Synchronous Register-Latch Mode, high-per-
formance CMOS Static Random Access Memories
(SRAM). These SRAMs are versatile, have a wide
input/output (I/O) interface, and can achieve cycle
times as short as 4.5ns. Differential K clocks are
used to initiate the read/write operation; all internal
operations are self-timed. At the rising edge of the K
clock, all address, write-enable, sync select, and
data input signals are registered internally. Data out-
puts are updated from output registers off the falling
edge of the K clock. An internal write buffer allows
write data to follow one cycle after addresses and
controls. The device is operated with a single +3.3V
power supply and is compatible with 2.5V LVTTL
I/O interfaces.
nrlL3325.00
08/06/2001
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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