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IBM041811QLAB-5 参数 Datasheet PDF下载

IBM041811QLAB-5图片预览
型号: IBM041811QLAB-5
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 64KX18, 2.5ns, CMOS, PBGA119, BGA-119]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 21 页 / 301 K
品牌: IBM [ IBM ]
 浏览型号IBM041811QLAB-5的Datasheet PDF文件第7页浏览型号IBM041811QLAB-5的Datasheet PDF文件第8页浏览型号IBM041811QLAB-5的Datasheet PDF文件第9页浏览型号IBM041811QLAB-5的Datasheet PDF文件第10页浏览型号IBM041811QLAB-5的Datasheet PDF文件第12页浏览型号IBM041811QLAB-5的Datasheet PDF文件第13页浏览型号IBM041811QLAB-5的Datasheet PDF文件第14页浏览型号IBM041811QLAB-5的Datasheet PDF文件第15页  
IBM043611QLAB  
IBM041811QLAB  
Preliminary  
32K X 36 & 64K X 18 SRAM  
Timing Diagram (Read Write Cycles)  
tKLKH  
tKHKH  
tKHKL  
K
tAVKH  
A2  
tKHAX  
A1  
A3  
A2  
SA  
A4  
tSVKH  
SS  
tKHSX  
tKHWX  
tKHWX  
SW  
tWVKH  
tWVKH  
tKHWX  
tKHWX  
SBW  
tWVKH  
tWVKH  
G
tGHQZ  
tKHQV  
tKHQZ  
tKHDX  
Q2  
D4  
Q3  
Q1  
D2  
DQ  
tKHQV  
tKHQX4  
tDVKH  
tDVKH  
tKHDX  
NOTES:  
1. D2 is the input data written in memory location A2.  
2. Q2 is output data read from the write buffer, as a result of address A2 being a match  
from the last write cycle address.  
©IBM Corporation, 1996. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
03H9040  
SA14-4659-04  
Revised 7/96  
Page 11 of 21